Practical Chip Design

One of the more interesting detailed conversations at DAC this year was with Teklatech, a small Danish company supplying a tool to improve dynamic IR drop and clock noise problems. Unlike analysis tools which simply identify potential problems, the Teklatech FloorDirector uses a combination of techniques to attempt to reduce supply current surges during the clock edges in synchronous circuits—thereby both reducing dynamic IR drop and noise in the circuits.

Dynamic IR drop has pushed its way to the front of designers' nightmares in recent years. Most CMOS clocked cells draw supply current primarily during clock transitions. Very fast clock pulses and very fast register designs have exacerbated this problem, resulting in huge current spikes with durations in the picoseconds. Unfortunately, this means that average supply current is an unreliable guide to the actually supply voltage change due to IR drop. If a design team has done a careful job of clock tree synthesis and reduced skews effectively, many cells will be switching almost simultaneously, and simultaneously swallowing deep gulps of current. So when it matters most, a cell may have much less voltage available to it than static IR analysis would suggest.

Just as bad, these very fast high-current spikes are wonderful sources of noise—again, much better noise sources than a static analysis might predict. This is particularly the case where there is series inductance in the supply grid—often hiding in the leads of a wirebond package. So understandably there has been a lot of interest in analysis tools for dynamic IR drop.

The normal way of dealing with dynamic IR drop is to make lots of current available from a local source, so the current spike won't have to flow through a long power-grid path or a wirebond loop of wire. Designers generally do this with decoupling caps—dummy cells with intentionally high gate capacitance—distributed as liberally as possible through the design. That's a great idea, maintains Teklatech CEO Tobias Bjerregaard—or at least it was a great idea at 130 nm. But, Bjerregaard points out, in advanced processes there may not be all that much unused active area in the design, so all those dummy cells will start increasing the die area. And in advanced processes, the dummy cells tend to have relatively high leakage current. Add dummy cells and you increase your quiescent current.

Teklatech's tool takes a different approach. Instead of adding capacitance to the power grid, the tool tries by several means, including floorplanning changes, retiming of pipelines, and working with available clock skew, to spread out the arrival of clocks to the synchronous cells on a power net. Done correctly, these activities do not impact logic correctness or timing closure (except for reducing the impact of dynamic IR drop on timing, thereby helping with closure) but they do reduce the peak current in the power net—by as much as 50 percent, according to Bjerregaard.

Perhaps just as significantly, spreading out the clock pulses across the available timing window reduces the first derivative of the current—by as much as two thirds, Bjerregaard says. That, of course, gives stray inductors far less energy to work with, and slips less high-frequency energy through parasitic capacitors. The impact on overall chip noise can be dramatic.

At the system level, these reductions can mean fewer decoupling cells, less supply metal, and even fewer supply pins on the package. (Or, alternatively, they can mean a die that actually works in the package that the cost-analysis folks said you had to use.) The FloorDirector tool comes into play during placement, and works with the rest of the flow as a native Open Access tool.