Practical Chip Design

Sep 18 2007 11:43AM | Permalink | Email this | Comments (1) |
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As pin-counts have grown, pretty much as predicted by Rent’s Rule, and signal speeds have increased, the cost of packaging has become once again a very significant portion of SoC cost. Add in the impact on board layout, the difficulties created by hard-to-find packages and limited access to high-end packaging, assembly and test facilities and higher failure rates, and there is good reason to reduce SoC pin counts. Sometimes better partitioning can help, but the main weapon in this battle has been the use of high-speed serial I/O to replace slower parallel ports.

But high-speed serial has its own problems. It requires PLLs, SerDes blocks, low-voltage differential signaling (LVDS,) and very careful board and package design. Now a new company, Align Engineering, is offering what the principals claim to be a far simpler alternative: the Align-locked loop. The approach in effect fuses two clock domains on two separate chips into a single domain, allowing designers to replace a pair of PLLs and a pair of SerDes with a bit of simpler circuitry and one clock-data-recovery block.

The technique looks very similar to things already done widely in telecommunications. It is a serial link, using a physical medium such as LVDS. But instead of being source-synchronous—that is, the receiver on each end has to reconstruct a clock from the incoming signal and lock onto it—the system synchronizes the transmitters and receivers to each other during a training sequence. The master side of a bidirectional link has a transmitter and receiver, and a phase controller. The slave side has a receiver and a transmitter and a phase adjuster. The master inspects signals looping back from the slaves, and sends the slaves commands—coded onto the serial link--to adjust their phase delay until the signal arriving back at the master is locked in-phase with the signal the master is transmitting. Now everyone is in phase.

Bryan Hoyer, chief executive of the company, says that with existing transceiver technology Align-locked loops can achieve data rates of around 622 Mbits/second, either between chips on a board or between remote sensors and ADCs over Cat-5 cable. The technique is completely agnostic to protocols, as long as there is a way for it to transmit its coded phase-shift commands.

Align sees initial application for the technology in a very specific area: serial interfaces on high-speed analog-to-digital converters, where the overhead of traditional source-synchronous LVDS is a serious cost issue. The bidirectional nature of the link would allow programmable functionality, such as a programmable-gain amplifier, to be included in the ADC without additional wires or pin-count.

From there, the company wants to explore providing both soft and (significantly faster) hard macros to FPGA vendors. Beyond that, cost-effective linking of coprocessors into CPUs or DSPs beckons. Since the company is just developing demo hardware, the implications of the approach in terms of signal integrity, interference and susceptibility are not altogether clear. But it bears watching.

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