Practical Chip Design

The promise of a synthesis tool that can transform a C-language behavioral description of a system directly into functionally correct RTL continues to dangle like a carrot before the hungry jaws of both SoC developers and EDA vendors. There is some evidence that the most recent generation of tools, such as those from Bluespec, may have edged closer to that goal, at least for some types of applications. Cadence's announcement of it's long-rumored C-to-Silicon (CtS) tool today will certainly add volume to the discussion, and may in fact add some concrete ideas to the pursuit of the goal.

The tool appears to arise from good stock. According to the company and other sources, the product group that produced CtS drew technology both from long-term studies of synthesis and database technology at Cadence Berkeley Labs and from synthesis work at 2003 acquisition Get2Chip. In fact, some staff from the corporate research lab appear to have transferred to the product team during the final phase of the development cycle. And the product team has worked closely with key-customer design teams, including at least designers at Hitachi and Renesas. Thus users could expect something based on proprietary research, not just a restatement of the current state of the market.

Cadence marketing people would like to reinforce that impression. The company is claiming a number of benefits that directly address complaints against the most widely used current ESL synthesis tools. The company claims high-quality results, comparable to, or in some cases superior to, the hand-crafted RTL of experienced designers. Striking directly at another criticism of ESL tools, Cadence claims that CtS automatically synthesizes control code as well as datapath code. And addressing a growing concern of design teams everywhere, Cadence says that CtS will allow far better predictability on critical design parameters such as performance and power, due to a unique link between the tool and Cadence's RTL libraries. And the tool offers an incremental synthesis mode that allows users to lock down portions of already-completed RTL to avoid resynthesizing an entire block to accommodate an ECO.

According to group marketing director Ran Avinun, CtS in its present form is intended for synthesizing a dialect of C++ into RTL at the IP block level, not for full systems. Thus it is not intended to be a system modeling tool or a system synthesis tool. It is intended for developing, making early estimates on, and synthesizing the RTL of digital IP blocks of limited size. "We see this as the tool you use for the blocks you develop internally, in conjunction with the IP you bring in from third parties," explained Mike McNamara, vice president and general manager for the new product group. "It would be used in conjunction with the traditional RTL IP integration flow."

The question of dialect deserves some comment. "We intend users to employ a subset of C++ to describe algorithms, within SystemC wrappers," McNamara said. "The subset is more comprehensive than is synthesizable in most tools today. For instance, we support pointers and casting. We don't support mainly run-time C operations such as dynamic memory allocation.

"Once customers have described their algorithms, they would use SystemC to describe transport and media protocols. This lets users define the entire system, including the interfaces with their control logic, in SystemC and C++, rather than having to select modules from a Wizard for the control functions."

Addressing the issues of results quality, and of timing-dependent control logic, Cadence turned to a proprietary development from their Labs: a comprehensive database. The database, which the company described as the crown jewels of the program, allows links between the various levels of abstraction for the design. This is a vital capability because CtS, unlike most existing tools, pulls detailed model data from the technology libraries used by Cadence's RTL Compiler (RC) for timing estimates. This, according to the company, both allows accurate design estimation from the C++ level and it permits CtS tool to use good estimates to perform optimizations, resulting in good quality of results. "Allocating hardware and scheduling operations have always been tough problems for ESL synthesis because they require accurate timing data," observed Cadence director of marketing Steve Svoboda. "That's one reason you see a lot of tools for datapath design, but few for control logic. We've tackled this by embedding calls to RC in the ESL synthesis tool. CtS is seeing the same data that RC will use later in creating netlists." In a rather telling aside, the Cadence spokespeople said that if you don't happen to be using RC for your RTL flow, your results may vary from those predicted by CtS.

CtS maintains strict separation between the functional description in C++/SystemC and attempts by the user to steer the implementation, Cadence says. The tool does this by having the user create TCL constraints that are kept as a separate batch file and processed along with the source code and the technology files when you push the go button. The idea is to give CtS the hints it needs to meet your design requirements by manipulating the constraints file, not the—hopefully reusable—C++ and SystemC.

An interesting point here. Rather than lock the source and TCL together with build scripts, Cadence has worked out a heuristic that, when it discovers that the source code has changed, attempts to associate the blocks in the constraints file with whatever blocks in the new source code are most appropriate. So if you rewrite a section of code, CtS will attempt to figure out what constraint TCL applied to the old block and associate it with your new block. McNamara refers to this as a "fuzzy match" capability.

Along the way to RTL, CtS emits two very important ancillary files. One, called a Fast Hardware Model, is a transaction-level model, using the "approximately-timed" mode of TLM 2.0, to provide cycle-accurate modeling at 80 to 90 percent of the speed of the SystemC model. This model is built, McNamara said, by using the technology libraries and the user's constraints file to create cycle-accurate models of the modules in the C source. The second output of interest is apparently still in progress. Cadence is creating scripts that will allow linking CtS directly to Calypto for formal equivalence checking of the C source and RTL output.

There is as yet no public user data on the CtS product. But it is unquestionably a formidable undertaking, addressing some of the most pressing problems users report today on ESL synthesis. The scope of this product and its R/D pedigree both suggest that CtS will be getting a lot of evaluations in the near future.