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Ron WilsonEDN Executive Editor Ron Wilson explores how IC design teams really work: the struggle for power efficiency and performance, wrestling with semiconductor processes and design methodologies, the challenges of global design teams. How do we somehow herd architecture, IP, design and verification into a successful tape-out?



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Friday, June 19, 2009

CPU power management, systems architecture and market share: a not-so-subtle interaction

Jun 19 2009 12:40PM | Permalink |Comments (0) |


An interesting thread of reasoning emerged at several different spots during the Research@Intel Day yesterday. The thread started with a passing mention, during CTO Justin Rattner's introductory remarks, of the substantial reduction in static power in the Moorestown CPU architecture. According to the CPU architect Rattner summoned to comment on the claim, this was achieved primarily by extensive use of power gating in the CPU.

But power gating is not a magic spell. It only works under the right conditions. Specifically, for power gating to actually save energy, the CPU has to know in advance when it will be able to shut down a section of the hardware for a considerable period of time. Otherwise, not only will the latency required to re-power the block interfere with processor timing, but the energy consumed in saving state, isolating the block, powering down, and reversing the process will exceed the energy during the down-time.

The problem here is that today neither operating software, nor applications, nor systems are structured to provide this information to the hardware. And so most of the potential benefit of power gating goes to zero in the real world.

But Intel has never been a company to let the real world interfere with a good CPU architecture—not when the real world can be changed. And so throughout the work Intel Labs teams showed off at yesterday's event, the theme of workload and traffic shaping kept popping up. The idea seems to be to shape network traffic and processor workloads so that any idle state in CPU activity has a very high probability of being a long idle state, making power-gating a winning strategy for energy conservation. If the system can actually identify the beginning of a long idle state and queue the operating software, that is an even bigger win.

Intel has, characteristically, come up with a name for this movement: platform power management. The low-hanging fruit is to simply keep pointless chatter at the board or system level from interrupting the CPU. This can be done by handling small tasks locally, either with intelligent DMA controllers and embedded low-power microcontrollers, for example. Decentralization pushes lightweight tasks that don't require CPU-scale processing power out into much lower-power hardware. It can also push temporary data structures, such as in-transit network packets or peripheral status blocks, out of main memory into local SRAM or Flash, preventing trivial transactions from thrashing the CPU core, DRAM interface and memory modules.

But the idea extends way beyond the platform. One exhibit at the event demonstrated how VoIP traffic from a local area could be collected and shaped into bursts by an intelligent network. These bursts would not only condense the packets in time—saving up packets until the first one absolutely had to be sent, and then sending a whole stream of them. It could condense packets in space as well—gathering packets headed for similar destinations into a burst that would traverse much of the network unopened, and only be split into smaller bursts as it approached its destination.

The bursting of packets saves energy in a big way, if the routers and end-points are heavily invested in power-gating and dynamic voltage-frequency scaling, both of which impose latencies and require relatively large minimum stand-down times. If a PC or smart phone knows that at the end of a burst that it is not going to receive another packet for several milliseconds, the power management circuitry can save a lot of energy.

This notion of temporal and spatial bursting becomes particularly important when you combine it with another technology Intel was showing off yesterday: virtualization across the cell-phone network. Suppose you have an application that is very useful—say, face recognition or best-route analysis—but too big to run on your beloved smart phone's application processor. What if you could partition the task and dispatch blocks of code and data to all of the idle smart phones that happen to be checked-in to the base stations in your local neighborhood? Virtualization of computing tasks across the cell network could put server-farm power—and potentially, database access—in your palm, with minimal effect on your battery life.

But that's only true if your handset isn't paying a big energy premium for all the traffic that will have to move between your and the other handsets during the setup and computation. And that, in turn, requires that network traffic, even at the local level, be shaped to optimize it for the power-management schemes used by the application processors on the individual handsets.

Exciting stuff to think about. But one message hidden between the lines is that such a vision of the network of the future requires that we develop standards for chip-level power management. The individual processors being managed must have a way of communicating their needs to the traffic-shaping facilities in the network. Otherwise, the whole scheme loses much of its ability to extend battery life, and therefore much of its appeal. Unless everyone uses baseband and applications silicon from the same vendor, of course.


Related entries in: Processors & Tools | Wireless | 


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