EDN Executive Editor Ron Wilson explores how IC design teams really work: the struggle for power efficiency and performance, wrestling with semiconductor processes and design methodologies, the challenges of global design teams. How do we somehow herd architecture, IP, design and verification into a successful tape-out?
Jan 28 2007 9:23PM | Permalink |Comments (2) |
It has been wonderfully amusing this weekend to watch the Keystone Cops routine in the non-technical media as hapless writers attempt to explain high-k dielectrics, metal gates and sub-threshold leakage to a general audience. Efforts have ranged from the determined but doomed to the utterly comedic. About the only message that all reporters seem to have gotten undamaged onto their pages is that Intel has an enormous lead in process technology, with IBM right on their heels. Unfortunately, that is probably the one part of the story that is completely wrong.
There is no doubt that the increasingly unfavorable trade-off between transistor leakage and drive current is a major issue, at 45 nm and beyond. But the notion that the only—or the best—solution at 45 nm is to introduce metal gates and high-k dielectrics is at the very least suspect. In fact, even Intel may find that in practice the move was premature, and that it will force them to work out yet another gate stack in order to move to 32 nm.
A number of data points is available. Texas Instruments, one of the first if not the first to begin describing their 45 nm process, opted not to use a high-k metal gate arrangement, preferring instead to make one more trip to the now-familiar well of increasingchannel stress. The company seems quite comfortable that they can meet their needs with conventional—if very highly stressed--transistors at 45 nm, at least in the early stage of the process life. TI does not rule out adding other transistor options later.
Other researchers have observed that if indeed something does have to be done to the gate stack, the Intel high-k/metal approach is only one of a number of options. For an interesting discussion of these options, see the Semiconductor International story by Laura Peters here. Serge Biesemanns, director of CMOS device technology research at IMEC, said last fall that at least three options appear viable: metal gates, fully-silicided silicon gates (FUSI) and stacked structures incorporating metal layers.
Even if one were convinced that metal gates were the right path, there is the question of materials. As Peters points out, Applied Materials guru Farhad Moghadam, who is in an excellent position to know, believes that there is still no one material that is clearly suitable for the metal in the pFET gate. This choice of metals—listed as a trade secret in Intel’s announcement—is probably where Intel’s secret sauce lies.
Yet nothing is certain in the world of semiconductor materials, even if you are Intel and can yell very loudly. As the industry’s experience with copper proved, there are things you only learn about a new material in production. And there is such a thing as deciding too quickly. Intel indicated, for example, that their high-k gate dielectric would be Hafnium-based. Yet Biesemanns last fall observed that a growing literature suggests that materials based on Zirconium or Lanthanum could well supplant Hafnium very quickly. Any change in either the pFET metal or the dielectric would send Intel back to the lab.
So why do they take the risk? One answer certainly is that they can. Since Intel supplies no outside customers from its advanced process lines, and since it enjoys near-monopoly status, it can live with disappointing performance or horrendous yields early in a product life without the situation being obvious to the outside world. Unlike virtually everyone else, Intel doesn’t have to get it right the first time.
Also, there is the matter of Intel’s fixation with AMD. The latter company arguable showed up Intel’s massive R/D budget and vaunted process technology with the AMD/IBM silicon-on-insulator process advances a couple of years ago. Intel has regained an edge, arguably more from circuit design techniques than process expertise, but that could be temporary. The company that yells louder would love to plant the idea of process superiority deeply in the press’s memory at a time when AMD is being rather quiet, which probably explains IBM's tit-for-tat press release. Whether the gambles involved turn out to be worth it remains to be seen.
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