Practical Chip Design

LSI officially launched a new era in disk read-channel technology this week with the RC9500: a new generation mixed-signal read channel intellectual property (IP) core cluster. The block, intended for integration with a drive vendor's IP to create a single-chip drive electronics subsystem, plants two milestones at once. The IP is LSI's—and possibly the industry's—first adventure into 40 nm. And it appears also to be the first application of a low-density parity-check (LDPC) algorithm in read channel products. LSI intends the IP for the coming generation of 500 GB/disk 2.5-inch, and 1 TB/disk 3.5-inch drives.

The 40 nm part is pretty self-explanatory. LSI director of product marketing Gordon Paulus said that the technology allows the read channel to reach 4 Gb/s within the power budget customers have specified. LSI is notably tight-lipped about its circuit designs, but one suspects that implementing the analog front end of this block at 40 nm was not without its moments.

To begin with, 4 Gb/s is no mean speed, even given the relatively much higher f_t of the process's transistors. At these speeds even minimal parasitics and small variations can sneak up on one. Compounding the design problem for the analog people is the fact that the whole game in read channels is about noise. The head/media designers will have pushed areal density until every hint of noise margin is gone, so there's nothing left over for the low-noise amplifier designers. But low-noise design at 40 nm—especially in IP, were you don't control the charge other circuits might be pumping into the substrate right next door—is an art. It would be easy for circuit designers to lose the whole advantage of the new LDPC algorithm in the analog section.

Finally, 40 nm has issues for LSI's customers as well, according to senior product marketing manager Dan Dolan. LSI's interface to customers using this IP will be its familiar ASIC model. But everything will go far better if the customer brings to the table a design team and IP that are ready for the rigors of a 40 nm design.

The other milestone is LDPC. This signal-recovery technique has been used for years in such areas as satellite communications, where signal-to-noise ratios (SNRs) are very small, and where no one minds that the receiver fills a rack and runs slower than real-time. Getting the algorithm into a manageable gate count and power consumption and getting it to keep up with a 64 Gb/s bit stream were challenges. But LSI claims that LDPC provides at least 1 dB of improvement in SNR—a major increment in the world of disk drives.

The algorithm required some new architectural thinking compared to previous read-channel DSP designs, Dolan said. In addition, LSI designers put work into adapting the algorithm to the signal characteristics they expected from the next generation of head/media designs, which are themselves still evolving.

"We believe LDPC will be necessary to deal with the SNRs of the next generation of head/media combinations," Paulus said. "And our customers seem to be agreeing," Donal added.