Practical Chip Design

Mar 24 2008 12:39PM | Permalink | Email this | Comments (2) |
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TSMC's announcement of a 40 nm process this morning raises some interesting questions. The most obvious is timing: the company only announced production of its 45 nm process toward the fourth quarter of last year, and now they are saying that they expect early customers to be taping out on the 40 nm process before the end of this year. So what was the point on 45 nm—was it just a temporarily-restrictive set of design rules to get a few early customers, such as Altera and Qualcomm going before the end of 2007? Or are there substantive differences between the "old" 45 nm and new 40 nm processes?

These are not the sorts of questions an authorized company spokesman tends to answer directly, so we may never know for sure. But we can infer a certain amount from the technical details of the program.

To begin with, the 45 nm-to-40 nm transition appears to have been planned and discussed since the outset within the TSMC and lead-customer inner circle. "Early customers engaged at 45 nm, and at least some of these will move to 40 nm," according to JC Huang, manager of advanced technology marketing at the giant foundry. "We believe that during 2008 the mainstream of advanced design activity will move to the 40 nm process."

In terms of technical differences, at the top level there are not many. Huang said designers could expect about a 10-15 percent improvement in circuit density, a 15 percent improvement in active power consumption, and about the same leakage power for a given design. Notice that there is no mention here of improved performance—Huang was comparing the 45 nm LP to 40 nm LP, where speed is nominally not an issue. Of critical importance to library and IP developers, "every design rule can be shrunk directly to the 40 nm LP process," Huang promised. "From a GDS-II point of view, we have no concerns about doing a direct shrink."

Of course that does not mean that the mask features will be a direct shrink of their 45 nm equivalents. All of the OPC decoration, critical-area repair, and phase-shift implementation that may be necessary at 40 nm happens inside TSMC's captive mask operation, so it is invisible to customers. Huang does appear, however, to be saying that the OPC process creates no new restrictions on GDS-II layouts that would block a straight shrink of 45 nm GDS-II features.

Beneath that level, there are some important process differences. Huang said that in order to keep the leakage current from increasing with the reduction in channel length, process engineers had to alter the channel implant profile of the transistors. In addition, the SRAM cell, in order to shrink along with the rest of the process, required considerable engineering. SRAM stability margin is one of the rarest commodities in the world at these geometries. "SRAM was the most critical part of the new process," Huang said. "We are confident that we have achieved the same performance and stability as at 45 nm, with what is now the smallest announced cell in the industry." In contrast, analog and I/O structures will not shrink at all, since for the most part they already use larger-than-minimum-dimension devices.

TSMC appears to have orchestrated library and IP development to mostly wait for the 40 nm version. "Early customers attracted some IP to 45 nm, and this should shrink without problems," Huang said. "This is a scenario we had already discussed with the IP vendors in our ecosystem." For cell developers, version 1.0 SPICE models—marking the official engineering freeze of the process—have already been released. TSMC expects to have its own libraries available in Q3 this year, with IP from other vendors following in Q4.

So what is this—a shrink, or a new process? One suspects, given what we know so far, that the 40 nm version is the original process that TSMC intended to develop at this node. It, after all, will have a G version, an RF module, an embedded DRAM module, and all the other goodies that come with a full process node. The 45 nm variant apparently will have none of these. So what was 45 nm? One again suspects: either the 40 nm process was delayed—possibly by excessive variations in threshold voltage—and the relaxed, 45 nm variant was pushed out on the original schedule; or 2008 was the internal schedule all along, and the 45 nm variant was created as a preliminary—dare we say Beta—process to meet the market needs of Altera and Qualcomm. One can suspect, but one does not expect to have one's conjectures honored by either confirmation or denial.

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