Practical Chip Design

Just in time to steal some thunder from the Common Platform Alliance's technology event, TSMC this morning disclosed some early information on the giant foundry's planned 28 nm process node. Since TSMC has declared 40 nm, rather than 45 nm, to be it's standard process at the current node, that will make 28 nm it's standard node for the nominal 32-nm level. In contrast, the Common Platform Alliance is treating 32 nm and 22 nm as standard nodes, and 28 as a half node.

We are talking about early information here. TSMC said that the initial version of the process would not be available for production until Q1 of 2010. For very early adopters, the company plans to start engineering shuttle runs by the end of this year.

In order to meet that deadline, TSMC has in effect divided the move to 28 nm into two separate tracks—one lower risk but with issues, and the other higher-risk but more in the mainstream of industry thinking. The lower-risk approach is the 28 lpt process, which stays with a conventional silicon-oxy-nitride gate technology and an enhanced version of conventional strain engineering. The later, higher-risk approach uses a high-k/metal-gate stack. By a rather delicate argument, TSMC claims that this sequencing will be an ideal process for the anticipated early adopters in the handset SoC space.

TSMC senior director of advanced technology marketing John Wei explained. "The primary difference for design teams between silicon-oxy-nitride and high-k/metal-gate is in dynamic power vs. static power. At 28 nm, the silicon-oxy-nitride gate unquestionably has higher leakage current. But it also has—and I think not everyone has talked much about this—substantially lower gate capacitance than metal-gate processes. That means that while the static power for a given design will be higher in the silicon-oxy-nitride process, the dynamic power at high frequencies will be significantly lower.

"Our customers are telling us that the next generation of smart media phones and similar mobile devices will have quite high active duty cycles. When you have so many features in one device—phone, broadband, camera, video player—most of the time the blocks in the SoC are either active or they are power-gated off. So leakage current is not such a large factor in battery life. Active power is—and active power is proportional to gate capacitance."

Consequently, TSMC sees value in getting the 28 nm node into production with a silicon-oxy-nitride gate stack as soon as possible for the benefit of mobile SoC developers. It is not clear how this choice will go down with FPGA vendors—notably TSMC's huge customer Altera, which depends on early access to a hot process to stay even with Xilinx. FPGAs in the past have had rather coarse-grained means for power-gating unused blocks of logic, and hence, with their huge gate-counts, the chips have been very sensitive to sub-threshold and gate leakage characteristics. Granted a full-custom design such as an FPGA can use tricks to deal with leakage. It is not clear that even the programmable back-bias techniques Altera uses in its current generation can fully compensate for inherently high leakage in the process.

TSMC does recognize that at some point customers will require the better channel control of the high-k/metal-gate process. And the second track in the company's 28 nm program, the hp process, will use this gate technology. But hp is not scheduled for production until sometime in the first half of 2010. Nor is this a firm date. "The risk to high-k technology is whether it will become manufacturable in the 2009-2010 timeframe," Wei explained. "We have settled on a specific formulation for the high-k dielectric and the metal stack, but there are still major issues in integrating new materials into the process flow at this advanced a node."

In other respects, Wei suggested, the 28 nm node would be very much like the current 40 nm node. TSMC will continue to use its low-resistivity copper deposition technology to reduce interconnect resistance variations, and will make evolutionary improvements to the intermetal low-k dielectric recipe, presumably mostly in barrier layers. As much a possible the company will preserve its existing transistor layouts, as it's current approach to strain engineering gives a more regular contact layout, and hence lower contact resistance variations, Wei said.

Library and physical designers will see more restrictions at 28, Wei admitted. There will be more restrictions on the pitch and regularity of the contact mask, which of course mean more restrictions on transistor design and layout. And there will be more restrictions in interconnect as well. But even considering the more restrictive design rules, Wei maintained that most users would see 50 percent greater SRAM density, and nearly twice the logic density, compared to today's 40 nm process. "These numbers assume the use of restrictive design rules, and the use of maybe 20-30 percent of an additional metal layer to help with routing," Wei said. Whether there will be an increase in raw performance is not clear.

Additional modules will come as add-ons to the base process. Wei said that in anticipation of such applications as single-chip phones, the company would put the necessary passives for RF in the base process. But a full RF module, with adequately-characterized transistors for real RF design, would lag the lpt process by a ways.

Whether TSMC's decision to spit the 28 nm effort into two different gate technologies was a strategic move or a reaction to problems with metal-gate process development is not clear. Nor is it really an issue for most users. The challenge, rather, will be for users to understand the use-models of their products well enough to assess whether they should adopt the high-leakage, low gate capacitance lpt process, or whether they should wait for high-k. With the latter's schedule uncertain, it makes an interesting dilemma.