Practical Chip Design

We offer the following note as a public service to the verification community and to the Accellera committee.

"Multiple industry studies have revealed that functional verification debugging, on average, has grown to consume more than 60 percent of today’s ASIC and SoC verification effort. Clearly, this is a topic the industry must address, and some organizations have done just that. Those that have adopted an assertion-based verification (ABV) methodology have seen a significant reduction in simulation debugging time (as much as 50 percent) due to improved observability. Furthermore, organizations that have embraced an ABV methodology are able to take advantage of more advanced verification techniques, such as formal property checking, thus improving their overall verification quality and results.

Accellera, which has spearheaded the standardization of assertion languages and libraries, is conducting a survey on how to improve its Open Verification Library (OVL) standard. Specifically, the Accellera OVL technical committee is interested in learning about your level of use of assertion checkers and suggestions on future enhancements to the OVL. In case you do not use OVL (or ABV), we want to learn what barriers are preventing you from adopting them.

The survey can be accessed at: https://www.surveymonkey.com/s.aspx?sm=Ks8gDZ_2bOQkIgDHceY8zAFg_3d_3d

Harry Foster, Accellera Open Verification Library Technical Advisor

harry_foster@mentor.com

 www.accellera.org"

Given the time and energy that Accellera has put into helping the verification community with its struggle, a few moments to take the survey seem like a minor repayment.