Practical Chip Design

In the just-previous post we discussed ARM's implementation of an ARM 1176 core in IBM 45nm SoI using a standard CMOS flow. Now we should continue coverage of this sessions at this week's IEEE International SoI Conference to discuss how that is possible.

In most respects, the differences between bulk and SoI are irrelevant to a cell-based design flow. If the cells are designed correctly and accurately characterized, then to the tools they are just ordinary standard cells, according to Synopsys's Kevin Kranen. But Kranen pointed out two important exceptions to this generalization, and Michael Jacobs of Cadence elaborated on a third. All three relate to the behavior of the notorious floating-body transistor in the SoI process.

In SoI, remember, the transistors live in a very thin layer of silicon directly above a layer of insulating material. So the transistor body—the portion of the transistor directly below the active channel region—is floating: electrically isolated from the rest of the die by high-impedance leakage paths. Charge that accumulates in this region during operation of the transistor, like the charge on a floating gate, tends to stay there until it is swept, it leaks, or recombination carries it away. Since most of these effects are dominated by switching and current passage in the channel, at any given time the charge on the floating body depends on the recent switching history of the transistor.

But that charge has an important side effect. Like back-bias in variable-threshold bulk processes, the charge on the floating body influences the threshold voltage, V_t, of the transistor. Depending on the switching history, the transistor might have a slightly higher or slightly lower threshold than nominal. And V_t, of course, influences drive current, which helps determine switching speed of a node. The bottom line is that a gate's effective delay could vary by 5 percent or so depending on the recent history of its transistors. Timing analysis obviously has to take this into account, and the V_t variation shows up in a few other areas as well.

The first step in dealing with history effect, Kranen explained, is in characterization of the cells. Normally there is one entry per process corner in the delay file for each cell. With SoI, you need two: max history and min history. Also, because V_t will influence the cell's ability to conduct noise from an input node to an output node, the cell views may need to include additional data for use in signal-integrity analysis.

Once the cells are characterized, max and min history just become two more process corners, Kranen said. They have no effect until it's time for static timing analysis. During STA, the two additional corners participate in the normal multi-corner optimization process. For instance to determine set-up slack on a path, you would use the fast history corner for the launch path, and the slow history corner for the capture path. For hold-time slack you would do jut the opposite. This worst-case approach tends to overstate the impact of history effect, but it is sufficiently conservative that no extra margining for the mysteries of history effect is necessary. Similarly, according to Cadence's Michael Jacobs, the additional corners are used in statistical static timing analysis with no changes to the tool.

There is one more area in which floating-body effect becomes significant, according to Jacobs, and that is signal integrity. When an SI tool is assessing the propagation of an aggressor transition into circuitry downstream from the victim node, the history-based variation in V_t makes a difference in the path's ability to propagate the glitch. In some cases this analysis is relatively simple, but Jacobs warned that more complex circuits require transistor-level analysis to get an accurate picture of noise propagation. For that reason ARM has included transistor-level data in their models for use by the Cadence Spectre analog simulator. Jacobs did not say whether the SI tools could invoke Spectre automatically, or for that matter how often it would be necessary. But he did say that with the use of transistor-level analysis in some instances SI accuracy was comparable to bulk.

Finally, Jacobs alluded to new routing rules that Cadence and ARM are jointly developing for the SoI libraries. He did not explain why they were necessary.