Practical Chip Design

If a lot of the buzz at SPIE last week came from the packed sessions on EUV technology, a lot of the serious note-taking was done at the papers on double-patterning. Not least among the sources of interest was a morning-long press session presented by Applied Materials on their view of the subject.

Double-patterning is one of those rubber-gloves-for-leaky-fountain-pens technologies that have been forced into the breach by the failure of EUV to materialize in a timely fashion. The idea is simple: if a mask layer has features that are too close together to image successfully, try splitting the layer up between two masks, with half the edges on one mask and half on the other. Assuming you have good enough overlay accuracy (which turns out to mean about three times the accuracy you would have needed with a single mask) you can then have two separate masks, each with printable features, and have the combined result end up printed on the wafer.

That’s the simple version. From here, things get predictably complex. For instance, there are at least three methods of double-patterning under investigation, according to AMAT’s presentation. First, there’s the obvious way. Deposit a hard mask, and overlay it with the usual BARC and resist. Expose and develop the resist. Etch the pattern into the hard mask. Then fill the whole irregular surface with BARC, planarize it, coat with resist, expose the second pattern, develop and etch again. The BARC ends up patterned with the logical AND of the two mask patterns. This approach has a bit of the brute-force to it, as it can end up being more than a dozen steps to produce one pattern in the hard mask.

Researchers are hard at work now trying to perfect an alternative idea: what AMAT’s CTO Hans Stork refers to as double-imaging. This is just like the previous story. But in double-imaging, you put one layer of resist on the wafer, expose it to the first mask, develop it, and then chemically “freeze” that pattern into the resist. Then you recoat the wafer with resist, expose the second mask, and develop again. If everything works, you are left with a coating of resist in a pattern that is, as before, a combination of the patterns on the two masks. But that process of freezing the first pattern is still being researched.

The problem with both these approaches, according to Stork, is that they cannot realistically reach the overlay accuracy or line-edge-roughness required for the most critical layers on the 32 nm node. Now “cannot” is a strong word in this industry, especially from a company that is invested in an alternate approach. But the experience with EUV has given “cannot” a lot more respect that it used to have.

So some researchers are beginning to look to a promising third alternative: spacer-defined patterning. AMAT appears to be backing this horse heavily. In this approach, you use normal lithography to create a feature. Then you create a spacer layer on the vertical sides of the feature in the normal way. But now you etch away the original feature altogether, leaving only the spacer bars sticking up from the surface of the wafer. These become the mask for creating a set of features at twice the pitch of the original. It’s a bit of slight-of-hand, but it is self-aligning, so it is not dependent on the overlay accuracy of the lithography equipment. There are of course issues with this approach too, and they are also being worked on.

The reason all of this is important to chip designers is that any form of double-patterning comes with a price for physical designers. For example, spacer-defined patterning works best for regular, one-dimensional repeated patterns, like the parallel bars that lithographers are always showing off at conferences. Unfortunately, such patterns only occur commonly in NAND Flash metal. They aren’t typical of other semiconductor devices. Even DRAM is more complex than that.

The other double-patterning approaches may have the opposite problem. They may work well for certain kinds of semi-regular patterns, but not at all in, for example, the regular two-dimensional arrays of contact holes common in memory structures and cell-based logic blocks.

As a generalization, all of these advanced patterning techniques will impose limitations on the kinds of patterns that can be printed in the critical layers. These limitations won’t be as simple as ordinary design rules—they will limit the kinds and locations of devices in the circuits. And this limitation may extend above the cell-design level, to limit placement of standard cells. There is work going on now to determine just what these limitations will be, and the answers are not in yet. But it’s a good bet the restrictions will require at the least hot-spot detectors that will scan a physical design and warn of unsuitable patterns.