Practical Chip Design

Jul 16 2008 5:17PM | Permalink | Email this | Comments (0) |
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Researchers, equipment vendors, and manufacturers alike are watching with growing concern as we creep every closer to the end of 193 nm optical lithography. The problem is not that there are no possible solutions to lithography in the range of the 35 nm half-pitch. The problem is that there are several possibilities, and none appears ready to step into the breach.

The obvious solution is a further extension of 193 nm technology. There is a clear roadmap that would turn today's immersion equipment into a production-ready stepper for the 35 nm half-pitch. We simply need either a multi-patterning technology or another step in numerical aperture (NA.)

Check item one. IMEC announced this week that researchers at that European organization have developed a variant to the double-patterning process that significantly simplifies it—in effect, that brings it near production-ready status. The trick, as described here earlier, is to expose the resist with the first pattern, apply a chemical enhancement to freeze that pattern into the material, expose the second pattern, and then develop and etch the resist normally. The big advantage of this approach, according to IMEC vice president of business development Ludo Deferm, is that the wafer stays on the litho track for both exposures. It doesn't have to go off to a separate etch track and then back onto the litho track. A small thing, perhaps, but a significant savings.

Unfortunately, the news on a larger NA is not so encouraging. Deferm says that researchers have not yet identified a suitable material with a high enough index of refraction to make the lenses. And even if the material were qualified today, the optical wizards say, there would not be time to develop a production-ready optical column in the two remaining years before 35 nm must be in production.

So we will go to the 35 nm half-pitch with essentially today's steppers. Beyond that is no man's land. It may prove possible, by extraordinarily aggressive OPC, creative illumination, and spacer-defined multiple patterning, to go one more node. But it will cost us. "Double-patterning today can already run the total budget up to as many as 70 masks," warns Synopsys manufacturing products group director Tracy Weed. The strain on databases, tools, and equipment is already significant. And higher resolution will create even higher stress on overlay accuracy.

So what next? Intel, ASML, IMEC, IBM, and many others have placed a lot of their chips on EUV. There's an EUV Alpha system up and making patterns in New York, and another at IMEC. But no one is pretending that these systems can be easily upgraded to production status. Today the illumination is far too anemic for production exposure times, there are still serious issues with the non-pellicle mask technology, and the system is the size of a good-sized truck. At this stage, it is also priceless.

Yet Deferm is relatively positive about the hopes for EUV in the question-mark land beyond 35 nm. The illumination vendors have announced a roadmap that, if it works, will take them to the tantalizing edge of production-level intensity. Whether they can stay on the roadmap—which skeptics claim contains a couple of "and then the miracle happens" inflection points—is an open question. The mask problems appear no more difficult that those solved for previous generations. Again, there are skeptics, who would say the mask problems are no more difficult than those that stopped 157 nm lithography dead in its tracks. But if EUV users can tolerate significantly shortened mask lifetimes and higher mask costs, masks might not be the problem.

Deferm makes the need for EUV perfectly clear. "For high-volume production at these geometries, there is simply no other alternative." Deferm does say that we may see a bifurcation of lithography at this point, however. Due to the crushing cost of EUV, we may see the world dividing into really high-volume fabs who run over 100K wafers/month and must use EUV, and everyone else, who simply can't amortize the systems. For the everyone else, Deferm suspects the answer may come from direct e-beam lithography.

Currently used only for mask-making, and for one prototyping facility at Fujitsu, e-beam is due for a significant upgrade. Programs in the US and the EU are pursuing multi-beam systems that can get throughput adequate for Deferm's moderate-volume fab lines. Perhaps the most well-publicized work so far is at Mapper Lithography. But no one is saying that operating 10,000 electron beams in parallel on random patterns at sufficient speed to make a production instrument is a solved problem.

That leaves the door open for one more alternative: imprint lithography. This possibility is dismissed by most experts, and for solid reasons. The process--coating a wafer with a polymerizable liquid, pressing a mold onto the surface, polymerizing the liquid by ultraviolet exposure through the back of the mold, and then withdrawing the mold--is fraught with problems. Particles get in the way. Bits of polymer stick to the mold. The force can be excessive, distorting the polymer. Overlay accuracy can be insufficient. As a result, many say that imprint techniques will only ever be used for circuits at relatively large geometries that are inherently high in redundancy, and therefore defect-tolerant.

But ever is a long time. Mark Melliar-Smith, CEO of Molecular Imprints argues that his company has made major steps in each of these areas, and is now moving in fact from development systems to production lithography systems for two major classes of clients: NAND flash vendors and makers of pre-pattered disk drive platters. "We expect by the end of 2009 to have a production system that can do 20 wafers/hour per head in a cluster configuration, handle 300 mm wafers, and achieve something like 15 nm overlay accuracy," Melliar-Smith says. He claims that defect density is already below 1 defect/cm-squared, and is headed for a tenth of that. "That is within the acceptable range for memory manufacture and for disk platters," Melliar-Smith observes.

But it's not good enough for non-redundant random logic. Yet a couple of things could happen that could make imprint technology a competitor here as well. One is continued intensive work on materials and processes to drive defect density down further. Maybe two more orders of magnitude is too much to ask, but with a lot of work it may be achievable. And as Melliar-Smith points out, if EUV starts to look like a bad bet, there will be very intensive work on alternatives.

The other trend is in logic design. Already at 40 nm design teams and foundries are beginning to accept the reality that because of lithography constraints, the critical first few layers of an IC must conform to restrictive design rules. In fact in some cases the critical layers will become a regular grid, not the random patterns we use today at all. In that case, it might make a great deal of sense to use imprint technology to produce the regular grid on the critical lower layers, and then to use metal alterations at higher layers—perhaps with a very fast e-beam system—to shift circuit patterns around failed devices. There could be redundancy at the transistor level that would be transparent at the cell or circuit level. Lots of work to do there, as well, and obvious problems. But if the redundancy problem can be solved in a way transparent to logic designers, as it has been already for memory, suddenly imprint technology appears in a new light.