Practical Chip Design

A panel moderated by EDN senior news editor Ann Mutschler discussed the relationship between yield management and IP use at the GSA IP conference last week. Two primary conclusions emerged from the discussion: that yield management has to be a three-way partnership between the chip designers, the IP vendors, and the foundry; and that the entire SoC landscape is becoming too rough for small IP companies to traverse.

"The role of IP in many designs has expanded beyond simple reuse to save development time," argued Yervant Zorian, VP and chief scientist at Virage Logic. "Today, we find design teams turning to hard IP in critical areas as a way of ensuring manufacturability for their chips."

But that responsibility can't rest lightly on the IP vendors. Zorian went on to list three actions IP vendors must take—coincidentally, based on Virage's product strategy—to be partners in the yield issue. First, he said, IP vendors must characterize their products in silicon at the process and design corners. Second, they must make structures that are known defect risks—such as memory arrays—repairable or reconfigurable. And third, they must ensure that IP users have adequate access to the IP—in silicon, not merely in simulation—not only to test it but to debug the chips that employ it.

Kurt Wolf, director of IP supplier management at TSMC, added a foundry view to the picture. "There is no way to entirely escape early yield issues in today's processes," Wolf said. "What we do is to encourage teamwork between the IP vendor, the chip designer and our own teams to identify problems as early as possible. This means that when a yield issue emerges, all three companies must work together in an unconventional way. With today's schedules it is necessary to do the teamwork first, and then resolve the business issues afterwards."

Wolf said that TSMC's IP team spends a great deal of effort on third-party hard IP blocks, establishing best-practices margins for the IP design, running corner lots, and so on. Then TSMC's product verification team engages with the chip designers on how that team is using the IP. The emphasis is not on identifying blame, but on optimizing the system. "Sometimes the best way to production isn't fixing the primary cause of the yield problem, but rather having everyone make adjustments to minimize the effects," he said. "And yes, that sometimes means making adjustments to a working process to accommodate a new situation, and then going back to previous customers and updating them on the new process center so they can adjust their designs to it."

One of the most challenging issues for all three parties appears to be establishing the corners in the first place. In earlier days there was the tacit assumption that the process corners—in terms of critical dimension extremes or even in terms of equipment tolerances—were the real corners. But increasingly today, the process corners may not be the extreme cases for a particular piece of hard IP. "We have an optional program at 90 and 65 nm that we have made mandatory at 45 nm," Wolf said. "Our team works with the circuit designers to make sure we understand the circuit sensitivities to the process variables, so we know where the corners really are for a particular circuit design over the process space. This can involve some delicate negotiations with the design team about how much they are willing to reveal to us. But we cannot just assume that TSMC knows where the corners are for a new piece of hard IP."

All of this joint effort is necessary, both speakers maintained, to bring a 45 nm SoC into production-level yield. But it is a substantial drain on all three parties. And that means it is not really accessible to smaller IP vendors or smaller fabless semiconductor companies. In response to a question from the audience on how small IP companies can play in this scenario, Wolf responded "Frankly, we are seeing a segregation between those who can and who cannot play in advanced processes. We have limited resources, and we have to look to our customers to get input on which IP companies we should be working with." The implication is that if an IP company is small, they will only be included in TSMC's world if a large TSMC customer wants them there.