Practical Chip Design

Stacked packages with DRAM dice piled on top of an SoC die or a broadband processor chip have become a staple in the cellphone handset business. But to date, most of these assemblies are done with wirebond interconnect between the dice, sometimes with redistribution layers, and so the number of connections and the ability to reduce the impedance of the wires have both been limited. Functionally, the stacked package is pretty much today just a way to reduce real estate.

But all that is changing. Researchers have been talking for some time about using flip-chip technology in combination with through-die vias and bumps on the backs of dice to create wireless stacks of dice. This approach, in which dice directly connect to each other, promises both very high numbers of connections between the dice in a stack and very low interconnect impedance. In conversation recently Drew Wingard, CTO at Sonics, suggested that this technology is now so close to within reach that at least a couple of major designs—from the handset manufacturers, naturally—are using it. And this could make a fundamental change in the relationship between SoCs and DRAMs.

Here’s why. Commodity DRAM chips have a number of separate and independent arrays of DRAM cells on each die. All of these arrays are multiplexed together to share one I/O port, so you can only talk to one—or one set, in some cases—of arrays at a time. But remove the limitations of wirebonding, a lead frame and a package, and it no longer makes a lot of sense to funnel all the activity of those arrays through a single multiplexed port. You can eliminate big drivers, use all the connections between dice that you want, and expose all the arrays directly to the system controller chip that needs the data.

It appears that this approach is being tried in the aforementioned projects. If so, it represents a major change in thinking by SoC architects, who have made an art out of blending the various sources of external memory requests from a multiprocessing chip into one coherent stream of traffic on a DRAM port. Instead of figuring out how to blend the accesses together, the architects now have to figure out how to use a substantial number of simple memory arrays in parallel.

It would also be a huge change in thinking for the DRAM vendors, who have been in the business of letting a standards committee define every external detail of the chip, leaving themselves free to invent the internals. In this venture there are no standards to rely on—there would have to be intimate understanding between the SoC developers and the DRAM developers about the electrical and timing interface on the arrays, the power limitations on the DRAM dice, and so on. What had been perhaps the most purely commoditized of semiconductors becomes a custom product.