Practical Chip Design

With the huge amount of attention that has gone into energy efficiency on new SoC designs, surprisingly little attention gets paid to one of the greediest energy consumers: chip crossings. This is even more surprising since the emergence of practical system-in-package (SiP) technology have increased interest in multi-chip designs of late. Too often, an SoC is specified with the usual collection of more-or-less industry-standard interfaces, a few programmable I/O pins, and that is the end of the discussion. When it becomes necessary to partition the SoC into two or more dice, and that partitioning cuts across a critical dataflow, there is trouble.

Just how much trouble can be seen in any number of recent designs. Connections between an SoC and an external FPGA—often serving as an application accelerator—seem to be particularly problematic, but similar issues can come up when a high-definition video stream passes between analog and digital chips, for example. Ad-hoc interfaces get dragooned into service in manners ranging from the ingenious to the heroic.

The most common example is the PCI Express bus. IP is readily available for a PCI Express interface, and some of it even works. This provides an easy path between chips with relatively high bandwidth. So a standard that was intended for mini-backplane use is becoming chip-to-chip interconnect.

Just how much this appropriation is costing us was illustrated last week in a paper by Rambus at ISSCC. The company is not announcing a new interface specification, but rather exploring just how much energy could be saved by designing a chip-to-chip high-speed interconnect for efficiency rather than expediency.

The paper describes an interconnect structure that is in many ways very conventional, but that still differs considerably from most of today’s practice. It uses 200 mV differential signaling—the team found that this level was more than sufficient for reliable transfers. The output structure is source-series-terminated with 50 Ohms, and approach that proved nearly four times more energy-efficient than CML at a similar data rate.

Another opportunity to save energy was in clock distribution, where the typical high-speed interface eats heartily. The Rambus team fabricated big inductors in the top two metal layers to build a resonant tank circuit for the clock—at substantial energy savings. Yet another example was the substitution of a phase mixer in the feedback loop of the PLL for the conventional phase rotators in the clock-data recovery circuit. One phase rotator, Rambus engineer John Poulton pointed out, can consume more power than the entire Rambus interface.

More savings came from moving low-bandwidth functions, such as adaptive equalization and input offset adjustment, from hardware to software. This allows what Poulton described as a “low-rent” CDR circuit, with many of the ancillary channel management functions shifted to software, where they consume virtually no energy.

The result is a high-speed serial interface, suitable for ganging for greater bandwidth, that requires dramatically less power than, say, a PCI Express link. As a demonstration, it serves as a heads-up to SoC architects: it’s not wise to just reach for the IP catalog when it comes time to think about interfaces. There may be user-visible benefits to doing some design work at the chip crossings.