Anablog

Sept 16 2008 was another great day at the Digital Power Forum. Rather than high-level plenary sessions and CTOs talking about when digital will go mainstream, they had the hard-core technical sessions. These gave me a lot more faith that digital power can deliver benefits that people will pay for. You can still check out  Forum Wednesday, see you there.

Now the morning sessions were aimed to data center power management, so I skipped those in order to get some work done here at the Domicile of the Future. That was OK because the afternoon sessions were three tracks, a power conversion track, a mission critical facilities track and an advanced component track.

Texas Instruments starred out the power conversion track, which seemed the most popular track in the afternoon sessions. TI outlined an ac to dc PFC controller. It used one of their C2000 series controllers, which is a DSP-based digital power controller. As I noted yesterday, PFC is a great application for digital power because the fundamental loop is 120 hertz. This design used a two-phase PFC architecture, followed by a full-bridge isolated power stage that had synchronous rectification on the secondary side. Now this is a neat application because it takes advantage of the fact that a DSP can output many phases for all these FETs. This design had 8 FETs, so that is a way to use all the capabilities of a DSP. Now the downside of any DSP solution is that it has an upper limit on how fast it can handle all the switching. This design had the PFC section switching at 100Khz and could shed one of the phases. I didn’t note the power section switch frequency and it does not seem to be mentioned in the presentation. There is a nice chart that shows the processor utilization, 74% with a 60 MHz clock and 45% with a 100 MHz clock. The full-bridge output is 90 watts at 90% efficiency. One of the main reasons to love this design is reliability. If you use separate analog chips for the PFC and power that might drive the parts count up. Now since the DSP needs power drivers that may be a factor—you have to compare your existing implementation, but if you can use fewer chips it is a good bet you will have better reliability. On the downside the DSP cannot run up a power system over 1 MHz so you will need larger caps and inductors. If going to a fast analog chip that allows you to take out tantalum and electrolytic caps and use ceramic, that should be better reliability even if you do have a couple more chips—nothing is worse for system reliability that electrolytic capacitors.

STMicro had the next presentation about a digital controller they make that can do pulse skipping for light loads and can auto-tune the system to help you pick the coefficients. The part also features a non-linear mode for better transient response. Now analog parts have had this pulse skipping or “burp” mode for a while. I think what ST is claiming is that the digital control can help alleviate the problems with burp mode like ripple voltage and current. The headache we have always had with burp mode is that the power supply might make an audible noise if the fundamental frequency drops below 20kHz and EMI may be a problem down at lower frequencies. If the controller can limit the ripple currents this may have a beneficial effect on EMI as well. The other thing this part does is auto-tune in order to establish the PID coefficients. The parts actually inserts a disturbance in the loop and then looks at the gain and phase and figures what the best coefficients are for your application. The whole thing takes less that 100 mS. This helps design the system, allowing you to try out both ceramic and tantalum caps. Now the downside to this are that tuning an analog controller is not really that hard—a tweak box with a pot and variable capacitor can tweak in most analog controllers. But if you don’t feel comfortable doing this it is hard to beat a chip that tells you its own compensation.

Next up Zilker had a presentation on how a digital power part can adjust switching frequency to improve efficiency. If the frequency it too low then the RMS current losses are higher. If the frequency is too high then the switching loss predominates. One thing that digital power can achieve is changing the compensation for these varying frequencies. Of course these factors also apply to analog designs as well. Once again, you will have to watch out for audible effects if the frequency goes too low and there are transient response issues and keeping ripple voltage and currents below limits. I think Zilker’s point is that a digital chip can adapt itself to all these different conditions. What you need to do is make sure your system works under the different frequency, compensation and loop transient response conditions.

The next presentation was from Ericsson Power Modules. They pointed out some implications for the supply chain due to digital power. They noted that a common supply might be shipped to the customer with the application software that configures the power supply for a given use. This allows the power supply manufacturer to reduce proliferation of part numbers and lets the user have more direct control of the features they want.

The afternoon session started off with ChiL Semiconductor. What I liked about his presentation was that the presenter, David Williams, was not a marketing type or IC designer, he was a power supply system engineer that has worked for power module companies. One neat thing David showed was that by reducing the gate drive voltage you can reduce the charge shunted to ground through the gate capacitance., He also showed efficiency improvements obtained by phase shedding. Now, both of these techniques can be done in analog supplies, so the real interest was when he described using a non-linear control loop in order to improve transient response. Now one thing to realize is all this transient response improvement talked about by chip vendors can also be obtained by adding a few capacitors to the output bus. The whole point is that you can reduce the cost of the system by taking out caps and using the controller to maintain transient response. I myself am a little worried about non-linear control of anything, but David assured me that the chip can be designed in, even if you can’t take a bode plot with a Ridley or Venible since the non-linear control prevents network analysis techniques. David agreed that he was used to seeing loop response, but insisted that you can look and the time-domain transient response and infer from the ringing how stable the supply will be.

Next up was Texas Instruments with a nice theoretical presentation on modeling a digital power system, with emphases on how the application software can help you determine the compensation. One thing I found interesting was when the presenter, Mark Hagen pointed out that the form of the various equations really represented the same thing whether you do PID loop, a direct-form digital filter or 2^nd order look-up table. I would think this would also apply to equivalence to a PID loop in an analog controller. What was fascinating was when Mark pointed out that rather than match the feedback zeros to the plant poles, you might want to reduce the Q by spreading the zeros a bit. This reduced the output impedance of the supply to the minimum and will improve transient response settling time. Once again, TI demonstrated that you can use non-linear control and have the chip application software auto-tune the system. All this auto tuning sounds great but it reminds me of the fuzzy logic days when the software weenies said you didn’t have to understand the system, the fuzzy controller would figure things out for you. I prefer to design things a bit more deterministically, but it sure is great to have the applications software figure out the coefficients so you can then vary them and watch what happens to the loop stability and response.

The last presentation in the power supply design tack was about digital current sharing. Analog Devices had a nice presentation showing the digital protocols that can be used to allow redundant power supplies to share the load. Most of this was geared to a system where one supply was the dominant output and would be out-supplied by another supply when the dominate supply failed. When I consulted at Schlumberger, IMB mainframe people cam in trying to sell us the same front end power system used in IBM mainframes. It was very impressive. They did not uses a dominant supply. They designed the supplies with high output impedance and they just shared by way of diode or-ing. They also took in three-phase power but only used two phases. This maximized uptime in the situation where one of the three phases failed. The supply module could still output its full power. They told me that they had a 1 million hour MTBF and I said that was not great shakes, that was calculated,. They corrected me and pointed out hey had one million of these modules out there so the MTBF was demonstrated, not calculated. Pretty impressive outfit that IBM.

Now I have to admit I was not too interested in the mission critical facilities track, I am told the data-center people have been using the same slides for a while. I will leaf through the presentations in the next few days. The third track, about advanced components was very interesting. Most of the presentations were about silicon carbide. The final presentation was from International Rectifier about their gallium nitride (GaN) transistors. I wrote about this last week when they were announced. There is a little more information, but no datasheets and no parts and they are not handing out the presentation to the media, which tells me they announced it way before they were ready, probably to demonstrate that the offer they got from Vishay did not adequately value the research they have done on GaN. The IR devices seem to be depletion mode devices that may have a driver built in that makes them look like enhancement mode devices. Although Michael Briere, the former IR CTO, said that they may sell depletion mode devices as well. As I suspected, the substrate is silicon, both sapphire and silicon-carbide are too expensive for power devices. What should give pause to all the aficionados of digital power is that Michael thinks that the higher speeds afforded by GaN transistors may obsolete the suitability of digital loops. He agrees that digital telemetry is great and will always be with us, but points out that for the very high speeds that GanN is capable of, the loop will most likely be closed digitally. It certainly adds another vector of complexity to the interesting problem of digital power adoption. Briere’s slides showed switching supplies at 4 and even 20 MHz. He told me that these speeds are enabled by both the low gate capacitance and low on-resistance of the GaN devices. At these high speeds it is doubtful any DSP-based controller could keep up, and the state-machine controllers might have a significant increase in power consumption. Still there is no reason to think that fast converters and digital paths can be put into the digital chips to provide for the faster switching frequency. Another approach is to let the regulator switch at 4 MHz but only adjust the PWM at a slower rate. IR says that production devices will be ready and the end of 2009. It will be interesting to see how digital power products handle this almost decade increase in speed.