Now Hear This!

The next step in processor design is based on simplicity, but it’s going to make engineers cringe and programmers wince.

That message resonated loud and clear at In-Stat’s Microprocessor Forum this week in San Jose. While the goal among processor designers is to consolidate lots of different functions onto a piece of silicon, accomplishing that microscopic task is anything but simple.

For one thing, much of this effort is being driven by the convergence between the business and the consumer world, and the consumers are firmly in control. They want to be able to hook into networks seamlessly wherever they go, whether it’s their office intranet or their home e-mail and voice mail. And they want it to happen easily, without a plug, with a display that’s sufficient for whatever task they need, and it all has to be done on a single battery charge.

From a processor standpoint, that means pushing the envelope on Moore’s Law with everything from high-k insulation to low-k films. And because it’s almost impossible to scale performance with a single core at 65nm and beyond, that also means multiple cores.  That’s where software programmers start scratching their heads and thinking about the good old days.

Processors traditionally had a very special purpose. They served as the foundation for operating systems, which in turn served to coordinate the functions of applications. In the past, their sole reason for existence was to provide extensions for the operating system, basically throwing the technology over the wall to the next group. But as more cores are added into the chips, the processors will run far more than a single operating system. They may run multiple operating systems, middleware, or any combination that’s necessary to achieve better performance for less power.

That’s where the complexity really starts getting out of control. While this may be a more efficient model from an energy consumption perspective, programming these devices will be so complex it will make programmers’ brains hurt. Intel executives said they don’t expect a compiler to be developed that will do this kind of stuff automatically. That alone should make getting products out the door quickly much more challenging, to say the least.

And that’s just the beginning. “No one core fits everything,” said Jim McGregor, director of semiconductor and enabling technologies at In-Stat. “And the core is not the only significant IP in a chip anymore. There’s also the interconnect and specific cores for memory hierarchy.”

Making matters worse, it’s tougher to get the same kinds of performance increases out of these chips that consumers have come to expect. Max Baron, principal analyst at In-Stat, said the future is now focused on two types of processors. One is dedicated to threads, which creates its own set of problems. He said threads are sequential, so sequence 19 cannot be executed before sequence 20, for example. What that means is the execution of these sequences cannot be run any faster at a single process node, such as 45nm, but will require the next generation to see an improvement.

The second processors are ones that can be highly parallelized, something that is highly dependent on the application being run. Server applications such as search have been parallelized for years, but bringing that to personal computers and other computing devices such as a cell phone is a new concept—and one that doesn’t work for all applications. It works for video, audio and cryptography, for example, but not for an Excel spreadsheet.

And all of this is in the name of simplicity.

—Ed Sperling, Editor in Chief