Perspectives From the Leading Edge

The Electronic Component Technology Conference (ECTC) , is sponsored by the IEEE’s Component, Packaging and Manufacturing Technology Society (CPMT) and the EIA (Electronic Industry Association). For the Component and Packaging community this is the pre-eminent conference on such topics during the year. Their 59th annual meeting was held last week in San Diego. Despite the economy and H1N1 “pandemic” 520 paid attendees ( down ~ 25 % from last year) gave 262 oral and 74 poster presentations in 36 technical sessions. Unfortunately many of the speakers from Asia...Read More

As we have discussed many times before, one of the important aspects of 3-D technology process flow is how you handle wafer thinning. A typical process flow for temporary bonding involves the carrier wafer and/or the device wafer being coated with an adhesive, bonding of the device and handle wafers, processing of the wafers and then removal of the carrier, hopefully without ever having to handle the thinned wafer.

In all options there are two main components: (1) the materials used as temporary adhesive; and (2) the automated equipment used to bond and debond the wafer. Material suppliers have all been trying to increase the thermal stability of their materials to allow for higher temperatures during the thinning and backside proce...Read More

Philips spun out its semiconductor division and a lot of its debt as NXP in the fall of 2006. Ever since then, parts of the company have been sold off to lighten this debt load. Shortly after NXP announced the joint venture of its wireless division with STMicroelectronics, and the subsequent sale of this venture to ST-Ericsson, last summer, its 150 mm wafer plant in Caen, France, was put up for sale.

This NXP site has a history in 3-D passive integration, having successfully launched RF-SiP modules based on its so-called PICS passive integration technology in 2004. Several hundred million modules have reportedly been sold since then. Despite this success, NXP announced its plans to sell this site in 4Q08. For our previous discussion ...Read More

Design, Automation and Test in Europe (DATE) was held this year in Nice, France, which is certainly a NICE place for a DATE. I think that’s two double entendres in one sentence, certainly a record for me.

As part of this year's conference, Erik Jan Marinissen, IMEC; Yann Guillou, ST-Ericsson; and Geert Van der Plas, IMEC held a session entitled "3D Integration – Technology, Architecture, Design, Automation and Test." Certainly apropos for this blog, nes pas?

During his keynote address on “The Promise of TSV,&...Read More

Many of you will have already seen the press release that Dresden will be the site of a Fraunhofer 3-D silicon research institute. I decided to dig a little deeper, so I contacted colleagues in Berlin and Munich to learn more.

The newest Fraunhofer center, All Silicon System Integration Dresden (ASSID), will report into old friend Herbert Reichl, head of Fraunhofer IZM, which has branches in Berlin and Munich. The focus of the new center will be on prior-to-BEOL (vias middle) TSV, silicon interposers, thin die integration and 3-D stack formation. The center's goals include:

• TSV in passive and active semiconductor wafers.
• Silicon interposer technologies for high-density wiring and the integration

Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) held its 2009 technical symposium this past Tuesday in San Jose with the theme, “Collaborate to Innovate.” Although I wasn’t there, I did get a complete debriefing from my colleague Jan Vardaman, CEO of TechSearch Inc., who was on hand.

Depending on your frame of reference, there were many things to be interested in. Despite our current economic times, TSMC vowed to continue spending on R&D. They are looking to add 300 R&D engineers to their current 1200, and add 90 design engineers to the current stable of 600. They plan to equip and ramp up their 40 nm fab line this year.

Close...Read More

In a recent posting (PFTLE, “3D IC at the 2009 ISSCC contd.,” Feb. 25, 2009), I discussed the Samsung presentation on DDR3 memory. Samsung’s Uksong Kang described the use of 3-D TSV stacking to overcome DDR3 performance issues that appear with traditional technology. As part of his presentation, Kang showed an application timeline roadmap.

A few of you have sent messages indicating that you had seen the EE Times article ("Samsung Devises 3-D DRAM With TSVs," Feb. 10, 2009) that concluded, “So, when will 3-D devices with TSV hit the market?" Acco...Read More

Before we move on, there were a few more presentations that I wanted to review from the IMAPS GBC (Global Business Council) [see PFTLE “IC Insights Predicts Fast Industry Rebound...,” March 15, 2009; and “Like Swallows Returning to San Juan Capsitrano,” March 20, 2009]. One of the main themes for this meeting was the 3-D infrastructure and how it is going to develop.

Amkor's Bob Lanzone had a nice slide comparing the different classifications of vias (shown below). The two vias-first options (before transistors and before BEOL) are confusing to people, and ...Read More

On Friday, March 27, the IEEE CPMT (Components, Packaging and Manufacturing Technologies) local chapter in Austin, Texas, held an all-day workshop on 3D IC integration. The mixture of local speakers and invited speakers tried to present a coherent picture of where things are and where they are going in 3D. Pictured below are the morning speakers at the conference.

Morning workshop speakers included...Read More

Continuing with the presentations at the IMAPS Device Packaging Conference in Ft. McDowell.

Jeff Perkins from Yole USA showed an interesting slide, shown below, from Freescale. It points out that, cost-wise, packaging now exceeds silicon for ready-to-assemble die. Not sure whether this is specifically for Freescale die or the industry in general (any Freescale readers out there, please post an answer to this below), but this is significant nonetheless.

Jeff also showed ...Read More

The “miracle of the swallows" takes place each year at the Mission San Juan Capistrano in CA. Each year on March 19^th the little birds are drawn back to their summer home where they rebuild their mud nests, which cling to the ruins of the old stone church . Visitors from all parts of the world gather to witness the return of the swallows. "Scout Swallows" precede the main flock by a few days to prepare the way for the main flock to arrive.

In similar fashion 3D IC practitioners assemble each year, in mid March, at Ft McDowell AZ for the annual IMAPS Device Pkging Conf (DPC). They are preceded, by a day, by the marketing and sales folks (scout swallows) who attend the IMAPS Global Business Council (GBC) to discuss th...Read More

By now I know that most of you have read the lead story coming out of the IMAPS Device Packaging Conference (DPC) that was posted on Semiconductor.net this past Thursday. Being your 3D IC blogger, and being at a conference with three days of parallel sessions on 3D IC business and technology, you probably expected I’d be pumping up 3D IC, but that was not possible in light of Bill McClean’s rah-rah economic recovery presentation to the IMAPS Global Business Council. There were mainly packaging professionals in marketing, sales and business development in attendance, but they clearly understood that their market does not come back till the chip market comes back and the chip market does not come back till the overall economy rebounds.

As we fall deeper into the world wide recession or what ever you want to call this financial mess we are in, we begin to see the lasting effect that it will have on our industry.

Some of the changes that have occurred in our industry and will continue to occur will significantly change the landscape forever. In hindsight, this is not something new . I thought it might be interesting to contrast the major IC players circa 1989 (per the 1990 ICE industry status report) with today’s major players (just reported by IC Insights)

...Read More

continuing coverage of the key 3D IC papers at the 2009 IEEE ISSCC.............

Toshiba

We have already discussed how Toshiba's commercialization of CMOS CIS with TSV launched this industry segment [ PFTLE , “Imaging Chips with TSV Announced for Commercialization”, 10/27/2007; “Toshiba CIS Camera Module Details, EVG & 3M Settle”, 12/22/2008 ] Toshiba has also made it clear that 3D stacking with TSV will be necessary to maintain and increase performance in hi...Read More

Information Overload

Before I fill you in on 3D papers at IEEE ISSCC (Int Solid State Circuits Conf) lets talk about information overload. Several of you have contacted me by e-mail suggesting that I index these blogs so you can access the information. Certainly searching through all the PFTLE blog titles is not the way to do this. I brought this issue up with Editor-in-Chief Laura Peters and she quickly pointed out what should have been obvious “... that’s what the search engine is for in the upper left hand corner where is says powered by Zibb". Sure enough it works. Please give it a try. What I have not been consistent enough about is using the acronym PFTLE in every blog (especially the early on...Read More