Perspectives From the Leading Edge

Over a year ago we announced that Toshiba was going into mass production of CMOS Image sensors with backside TSV [ PFTLE, “Imaging Chips with TSV” 10/27/2007]. Since then, as you know if you read these blogs, most of the other major CIS players have followed suit.

In September Chipworks, a reverse engineering analysis company , announced that they had found the Toshiba TCM9000MD camera module which contained TSV inside a mobile phone and, working with Yole Development, issued a full reverse engineering report on the technology.

Yole has now divulged some of the key information in their Dec 2008

“i-MicroNews” newsletter [www.i-micronews.com ] which is always full of interesting 3D integration and packaging information.

I strongly suggest you go to their site and read the entire piece, but I will draw some of my own conclusions here on the photos and cross sections that they have presented.

Below we see a top down shot of the CIS chip showing that < 20% of the chip surface is taken up by the actual sensor. Thus, although the TSV are reportedly allowing Toshiba to shrink the overall chip size by 73% vs non TSV analogs, the “fill factor” is still very low and this chip begs for true 3D integration where the logic circuitry would be moved to a separate layer and bonded.

In the device crosss section shown below someone forgot to adjust the 20 um marker when they adjusted the picture size because these are not 10 um vias !

None-the-less a great cross section showing the relative thicknesses of the IR filter, support glass and CIS die as well as the RDL and bumps.

In the close up cross section of the TSV shown below we can confirm for the first time that they are using oxide insulation (not organic like ST Micro) and are filling the plated via with “organic” material. I would assume this is “filled” to adjust the CTE, but it is unclear from what is described or shown. Going by the 20 um marker, the vias are ~ 75 microns wide and 90 um deep which is about what we exected.

Yole goes into detailed discussion about whether the vias are Bosch etched or laser etched followed by photolithograpgy /dry etching of the “pedastal layer”. My interpretation is that the first etch or laser drill (whichever) stops on the oxide and the subsequent cut which looks like its photodefined is through the oxide to the backside of the pad. Any other thoughts on this ?? Lets discuss.....................

3M AND EVG SETTLE PATENT INFRINGEMENT SUIT

This summer we indicated that EVG had filed a patent infringement lawsuit against 3M [ PFTLE, “Recent Activity on 3D IC Integration”, 07/28/2008]. It was clear that it concerned the 3D patent 6,792,991 “Device for Detaching a Carrier from a Semiconductor Disc” . The newswires now indicate that 3M and EV Group (EVG) “...have agreed to settle the patent infringement litigation relating to systems for temporary wafer bonding.”

Under the terms of the settlement, the details of which are confidential, 3M, its customers, and 3M’s licensed suppliers of 3M's Wafer Support System will continue to make, sell and use the Wafer Support System in global semiconductor and packaging markets. EVG will continue to defend its patent portfolio and protect its intellectual property. I think that is legalese for 3M paid up, but we are not going to tell you how much.

Anyone who has looked at the IP landscape in 3D Integration knows that it is a vast minefield with patents going back to the mid 1980s so I expect a lot more of this kind of activity in the future.

.........................Merry Christmas and Happy Holidays to all................................

Thanks for your support during 2008. I promise more interesting material to come in 2009.

For all the latest on 3D IC integration stay linked to Perspectives From the leading Edge, PFTLE.................................