Perspectives From the Leading Edge

Design, Automation and Test in Europe (DATE) was held this year in Nice, France, which is certainly a NICE place for a DATE. I think that’s two double entendres in one sentence, certainly a record for me.

As part of this year's conference, Erik Jan Marinissen, IMEC; Yann Guillou, ST-Ericsson; and Geert Van der Plas, IMEC held a session entitled "3D Integration – Technology, Architecture, Design, Automation and Test." Certainly apropos for this blog, nes pas?

During his keynote address on “The Promise of TSV,” Sitaram Arkalgud (Sematech) presented a very handy graph on via resistance vs. dimension for p-Si, W and Cu vias (shown below). For instance, if you want to find the resistance of a 10 µm via in copper, just go up to the solid green line and to the left to see that it's <0.01 Ω. Continue up to the dotted green line to see that this is for 70 µm thick Si, or a 7:1 AR.

Riko Radojcic’s Qualcomm presentation included a very interesting comparison between various options for interconnection memory and logic. The three scenarios involve normal connection on a PWB, bonding commercial memory using an RDL layer and TSV, and using custom memory with matched I/O and TSV. Scenario C results in 3× less capacitance than scenario A; scenario D results in 10× less capacitance than scenario A; scenario C results in 5× less delay than scenario A; and scenario D results in 25× less delay than scenario A. These are very significant differences.

Nomura from Toshiba has conducted a simulation on a 16-core processor to quantify the impact of 3-D circuits in 90, 65, 45 and 32 nm CMOS technology. Based on the layout analysis of the 3-D circuits, the area overhead due to the presence of the TSV is less than 3%, when the diameter of TSV is less than 10 µm.

The improvement of 3-D to 2-D becomes larger with increasing cache capacity since the larger dimensions result in a longer interconnect path from the cache to the processor element. In these cases, the 3-D circuit has a big advantage in terms of improvement of processor performance.

The improvement ratio of 3-D to 2-D also increases as CMOS scales. This is due to the interconnect delay increasing with CMOS scaling as we have described previously. In particular, there are many cases of an improvement ratio exceeding 20% for 32 nm CMOS technology, which is attributed to large interconnect delay. This 20% improvement is close to that obtained by CMOS scaling for one CMOS generation.

Clearly, 3-D in 65 nm CMOS technology is superior to that of the 2-D system in 45 nm technology, and that performance of the 3-D system in 45 nm CMOS technology is superior to that of the 2-D system in 32 nm technology as shown in the figure below.

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