Perspectives From the Leading Edge

In a recent posting (PFTLE, “3D IC at the 2009 ISSCC contd.,” Feb. 25, 2009), I discussed the Samsung presentation on DDR3 memory. Samsung’s Uksong Kang described the use of 3-D TSV stacking to overcome DDR3 performance issues that appear with traditional technology. As part of his presentation, Kang showed an application timeline roadmap.

A few of you have sent messages indicating that you had seen the EE Times article ("Samsung Devises 3-D DRAM With TSVs," Feb. 10, 2009) that concluded, “So, when will 3-D devices with TSV hit the market?" According to Kang, the article reported, the timetable was 2008 for CMOS image sensors, 2010 for high-density flash and DRAM, 2012 for logic and memory, and 2014 for multilevel 3-D (systems-in-a-package) SiPs. This was repeated the next day by I-Micronews.

So why did I not comment on this Samsung roadmap? Well, I recognized it as one that has been shown/published by a marketing company at several meetings in the past few years. To me, it was obviously not a Samsung roadmap.

To ensure this was the case, recently I had a colleague with excellent connections in Samsung contact Kang. “The timeline I presented at the [ISSCC] is not a roadmap of Samsung Electronics. It's rather a general available roadmap [published by others]," Kang replied directly. "Even though there is big potential for TSVs to create new applications, high cost is an obstacle which needs to be overcome.” So I’ll stand by my more conservative predictions — NO 3-D NAND FLASH IN 2010!

Having said that, I must report that there are rumors circulating that Samsung will be sampling TSV stacked DRAM to IBM in the next few months. If anyone else has heard this, please comment below.

AMAT — one-stop shopping for a 3-D line?

If you were a major equipment supplier like Applied Materials and were hearing that the 32 nm node may be the end of the road for most of your current customers, what would you be doing? It’s no coincidence that Applied is investing heavily into solar and 3-D IC.

Applied supplies etch, dielectric deposition, physical vapor deposition (PVD) and chemical mechanical planarization (CMP) systems, but not the other equipment needed for a complete 3-D line. Applied’s strategy appears to be to partner with other leading equipment suppliers to offer the customer a complete equipment set for 3-D IC fabrication.

We have previously discussed Applied’s entrance into this area and its partnership with Semitool for copper plating (PFTLE, “3D Integration Stays HOT at Semicon West,“ Aug. 13, 2008). Then in late February, Applied officially joined the EMC-3D consortium as I had earlier predicted. Now, late last month, Applied announced a joint effort with Disco to develop wafer thinning processes. The two companies expect to develop wafer thinning and post-thinning processes of wafers bonded to silicon and glass carriers.

Will Applied become the “big cahuna” in 3-D IC equipment? The strategy appears sound. We’ll see whether this pays off for them.

Cu-Cu non-thermocompression bonding from Soitec?

Soitec, which before the recession employed about 1000 people worldwide, was created in 1992 by researchers from CEA/Léti, the French microelectronics research institute. Soitec is a major player in the silicon-on-insulator (SOI) wafer industry.

Soitec recently announced that its circuit stacking technology called Smart Stacking is ready for technology transfer and manufacturing. This technology was originally developed at Tracit Technologies, itself a spin-off from CEA/Léti that Soitec acquired in 2006. Smart Stacking involves the transfer of thin layers of processed wafers onto a variety of materials. It uses low-temperature wafer bonding, and reportedly the only surface preparation that is required is a standard CMP. Soitec says the technology can be used for wafer-level circuit stacking such as high-pixel-count image sensors, RF circuits, and more complex 3-D product architectures.

Bernard Aspar of Soitec has indicated in communication with SI contributing editor Ruth DeJule that Soitec, in partnership with CEA/Léti, is also developing a low-temperature non-thermo compression copper-copper bonding and alignment process. In fact, we have discussed this technology previously (PFTLE, “3D Practitioners Assemble at Ft McDowell,” March 23, 2008; "IITC on the 3D Integration Bandwagon," July 7, 2008; and “Fisk, Buckner and Pasta in the North End,” Dec. 31, 2008). Checking these articles reveals that indeed Soitec and STMicroelectronics supported the Léti research, so it now makes sense that they have access to scaling it up.

As you know, I am a supporter of non-thermal compression M-M bonding such as developed by Ziptronix (PFTLE, “Opening the Kimono, Ziptronix Gives Details on DBI Process,” Oct. 13, 2008). Such technology is required to increase throughput vs. standard thermocompression bonding in order for copper-copper bonding to become a viable economic option. It will therefore be of great interest to see how Soitec and possibly STMicro will move forward with this.

Economy affecting future of fan-out packaging?

Rumor has it that all the great work done at Freescale by Beth Kesser and her colleagues may come to naught. Evidently, the economic hit on Freescale is causing the chipmaker to look at licensing rather than commercializing its Redistributed Chip Package (RCP). Reportedly, the leaders for license right now are unnamed secondary players in Singapore and Korea. Word was that Intervia dielectric from RHEM (now Dow) had won the first-generation material battle for inclusion in RCP, but now the process is just part of the license package.

Their competition, the group including STMicro, Infineon and STATS ChipPAC that is aligned to develop Infineon’s embedded wafer-level ball grid array (eWLB) technology (similar in concept and structure to the Freescale RCP) appears to be proceeding as scheduled. It appears the leading dielectric candidate there is JSR’s WPR grade material, which is Novolac-based.

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