Perspectives From the Leading Edge

Continuing with the presentations at the IMAPS Device Packaging Conference in Ft. McDowell.

Jeff Perkins from Yole USA showed an interesting slide, shown below, from Freescale. It points out that, cost-wise, packaging now exceeds silicon for ready-to-assemble die. Not sure whether this is specifically for Freescale die or the industry in general (any Freescale readers out there, please post an answer to this below), but this is significant nonetheless.

Jeff also showed us Yole’s June 2008 projection for 3D IC wafer starts by application. Each bar we are told is 2 million wafers, resulting in 2012 total 3D wafer starts of 6-7 million.

Thought it would be interesting to compare to the numbers they presented last year this time, shown below (see PFTLE, "More 3D IC Integration From Ft. McDowell," March 30, 2008). Although the total wafer numbers are about the same, the CIS segment seems to have grown while the memory segments (both DRAM and flash) appear to have decreased substantially.

The equipment market is projected to become a billion-dollar market in the 2012-2013 timeframe with the materials market achieving that plateau a few years later. My guess would be that these numbers are derived as a percentage of total market value, not a bottoms-up customer-by-customer calculation, since such numbers just do not exist. If that is not correct, please feel free to comment below.

Bob Foreman, gristly veteran of RHEM (soon to be Dow Chemical), gave an interesting presentation entitled “Simultaneous Copper Electroplating of TSV and RDL Formations on 3D Wafer Structures Using a Highly Conformal Copper Plating Process.” The premise is that a uniform Cu overburden can be patterned and etched to form the RDL circuits after Cu via plating.

In terms of the etching he pointed out:

• More control of etch rate is needed for RDL Cu etching to minimize undercut effects.
• Cu RDL etching requires more control of etch rate.
• Typical UBM etches are too aggressive for precision RDL etching.
• RDL structures can be as small as 10 µm in width, whereas most UBM structures are hundreds of microns in diameter.

If you're in the Austin area, I’ll be presenting at the IEEE CPMT sponsored Workshop on 3D packaging taking place in Building C, Freescale facility on W. Palmer Lane from 8 a.m. to 5 p.m. Nice lineup of speakers and puts me close to my granddaughters in Houston for the weekend!

For all the latest on 3D IC Integration, stay linked to PFTLE………………