Perspectives From the Leading Edge

Tezzaron Semiconductor, one of the pioneers in 3D IC integration,  specializes in high-speed memory products. We have discussed their 3D wafer stacking processes previously [see PFTLE “More 3D IC Integration from Ft McDowell”, 3/30/2008; “Road Trip Continued”,05/28/2008]  Their Supercontact™ technology shown in the fig. below is a vias first, fab based, W TSV technology which provides very high density interconnect. 

For those interested in building prototype 3D-IC logic devices, Tezzaron has just announced a multi project wafer program. Up to ten participants will design two-layer logic devices to be built and bonded on the shared program wafers. Optionally, each resulting two-layer device may be integrated with a Tezzaron 3D-IC DRAM device. Both the logic stack and the DRAM integration will use high density interconnect ( their Supercontact technology)  “…in order to examine global I/O and memory bandwidth capabilities in 3D-ICs”.

Unlike University or Institute multi-project wafers, Tezzaron claims that these prototype studies can lead “…directly to commercial production”  since they are using a 130nm commercially available semiconductor process at a recognized international fab to manufacture the devices. Tezzaron has not announced the identity of the fab, but it is known that they have implemented a process  with Chartered in the past [ see PFTLE “50$ Bonding on the Horizon, Intel announces - We are ready", 10/29/2007]

Participants will have access to R3Logic 3D-enabled layout tools and a design kit created and supported by North Carolina State University. Wafers will be bonded by Tezzaron with a Cu‑Cu thermocompression process. Tezzaron will also provide 3D DRAM devices for integration, employing the IMIS standard published by the 3D-IC Alliance [ see PFTLE, “Recent Activity on 3D IC Integration”, 07/28/2008]

Participants will pay $1000 per square mm of wafer space. Interested parties are invited to propose any two-level logic device that can take advantage of high density vertical interconnects and/or high-speed memory bandwidth. Participants will be selected by the end of February, with manufacturing scheduled to begin in October. Readers with interest should contact Tezzaron directly.

For all the latest on 3D IC Integration stay linked to PFTLE……………………………………..