Brian's Brain

Sep 21 2007 10:17AM | Permalink | Email this | Comments (1) |
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To set the stage for the material to come in this particular post, I want to reiterate a point I made last week in the comments section of a previous writeup:

Regarding AMD vs Intel, I agree that healthy competition benefits everyone: suppliers, partners and customers alike. And I think that many of my Intel contacts would even agree with me, although they wouldn't necessarily be willing to go 'on the record' with their comments ;-)

With that perspective calibration check out of the way, I've repeatedly made the point in recent-past AMD writeups (see here and here, for example) that the success of AMD's 'Barcelona' quad-core Opteron and follow-on K10 microarchitecture-based products such as Phenom will be heavily dependent not only on AMD's actions but also on the rapidity and voracity of competitor Intel's reactions (and proactive actions). Specifically, I'll be closely monitoring how strongly Intel's 45 nm process (and products based on it) ramp. If this week's IDF forecasts are indicative of the company's near-future feats, I frankly suggest that AMD's Hector Ruiz immediately purchase large bottles of Rolaids and Tylenol.

Beginning in 2001, Intel began executing on a 'right hand turn' CPU strategy championed by then-COO (and now-CEO and President) Paul Otellini, which de-emphasized per-core clock speed in favour of a focus on increasing the number of cores per die and per device (via multi-die packaging techniques). This corporate shift was the result of two primary factors:

• A realization that leakage current-induced power consumption at sub-100nm lithographies would result in an impenetrable (practially speaking) clock speed ceiling, and
• An acknowledgement of the market share gains that competitor AMD had made with its K6 and K8 microarchitecture-based chips, which on average delivered more power-efficient performance per clock tick.

The effect of the 'right hand turn' was most publicly communicated via the cancellation of the NetBurst-based Tejas (Pentium) and Jayhawk (Xeon) programs in May of 2004. As Steve Smith, Intel's Corporate VP and Director of Group Operations for the Digital Enterprise Group, explained during his 45nm Product Press Briefing on Wednesday, the fundamental intent of the 'right hand turn' was two-fold:

• To align the company's various market (and consequent product) focuses: handheld, laptop, desktop, workstation and server, along a common CPU microarchitecture vector, acknowledging that performance-per-watt had become a dominant issue across them all, and
• To better synchronize microarchitecture and product-based-on-microarchitecture transitions to underlying process transitions.

The end result of the 'right hand turn' is Intel's oft-promoted 'tick tock' approach, which:

• Makes a significant lithography migration in combination with a comparatively minor product alteration (tick), then roughly one year later
• Makes a more substantial microarchitecture evolution, on the same process as before (tock)

Said another way, process and microarchitecture transitions would both run on two-year cycles, but one year offset from each other, to minimize the risk as compared to a simultaneous lithography-and-architecture shift.

Continue reading with 'The Intel Developer Forum: 45 nm Now, Nehalem Next Year, 32 nm In Two'...