Brian's Brain

Late last week, in an email-based discussion between several of us on staff, I commented that I strongly suspected AMD would do a core count-slimming die 'chop' of its quad-core Opteron as part of the design's evolution to the consumer-targeted Phenom K10 microarchitecture variant. I made this prediction for several reasons:

• To the degree that AMD may be experiencing limited yields on its relatively new 65 nm lithography process due to die defects, a smaller die would exponentially increase those yields. AMD could alternatively construct a quad-core chip, as Intel does, by putting two dual-core die (in this case interconnected via a HyperTransport link, versus front side bus-connected as in the Intel case) within a single package.
• Removing CPU cores from the die layout would free up room for AMD to alternatively beef up each chip's L1, L2 and/or L3 cache sizes (see the die photo on AMD's website for an indication of how much space each core takes up).
• Although much of today's workstation software is multi-threaded, as is server-class code (which, by virtue of the number of clients simultaneously contenting for any one server's attention, also operates in a multi-core-friendly multi-task environment), few consumer-class applications have been multi-thread transformed or from-scratch crafted, or frankly are capable of substantially benefiting from such optimization. A fewer-core Phenom would not only be less expensive than its quad-core sibling, it'd also more directly target today's consumer PC 'sweet spot'.

I suspected AMD would first do a dual-core deletion (and still suspect it will sooner or later) subsequent to rolling out the quad-core Phenom premiere product...but last weekend I started hearing rumours of a three-core Phenom (i.e. a single-core chop) and last night AMD made it official. There's no fundamental reason why such a design wouldn't be useable (reference the Xbox 360 as a comparative case study), of course; AMD just needs to reconcile the cost and yield of the resultant die layout against the market demand for such a product (and therefore the price that customers would be willing to pay for it). And PC prior art exists, albeit in a triple-CPU system configuration (with a single-hop interconnect from any one CPU to another over HyperTransport, thereby explaining its appeal) versus the triple-core single-CPU scheme that I'm discussing here.

The resultant die layout will, I suspect, be a bit odd...rectangular (which, granted, plenty of memory chips have also employed over the years), versus square...unless as I suggest above, AMD alternatively devotes the die area freed up by the core deletion to added cache. This'll be interesting to watch, and I'm also curious to hear Intel's reaction at the Developer Forum I'm headed to as soon as I press 'post' on this writeup.

p.s...my first thought when I heard the initial three-core Phenom rumours over the weekend was that AMD's move might reflect poor quad-core functional or speed yields i.e. AMD might be shipping quad-core die with one no-pass-test core disabled as Sony does with the SPE-disabled Cell processors in the PlayStation 3. I haven't convinced myself that this isn't behind what AMD's doing, but as a quick perusal of the earlier-mentioned 'Barcelona' die photo will show, AMD would be shipping a lot of zero-revenue faulty-single-core-containing silicon in such a scenario. Then again, though, if AMD is alternatively being forced to discard a lot of zero-revenue faulty-quad-core-containing silicon...(my exact words in Sunday's email to my EDN cohorts: "Having one inactive CPU core sitting on the die would be one h*ll of a silicon area hit...unless they're alternatively throwing away one h*ll of a lot of silicon")