Brian's Brain

This blog post references my cover story 'Embedded x86: Keystone Of Your Non-PC Design?' in EDN's May 29, 2008 edition. It's one of a series of web addendums to the print writeup.

Any discussion of Intel and Via's respective processor offerings naturally also cultivates thoughts of the third major x86 CPU supplier, AMD. Like its competitors, AMD is plenty busy this week at Computex, finally rolling out its Intel Centrino-targeting Puma platform. How I detest these tedious multi-stage rollouts...AMD first publicly discussed its 'Griffin' CPU more than a year ago, and the Puma platform received its first unveiling in early March.

As review, Griffin (now known as the Turion 64 X2 Ultra) is a 65 nm lithography-shrunk follow-on to prior-generation Turion-family CPUs (although AMD is in the process of moving all of its products to 65 nm), with several key advancements: twice the L2 cache (now 1 MByte per core), HyperTransport 3.0 connectivity, and multiple on-die voltage planes. To clarify; it's not a K10 (aka Barcelona and Phenom) microarchitecture-based CPU, which means that like Intel's current CPUs, it offers a maximum of two cores per die (versus three or four). However, although it may be core count-competitive with Intel's products, it's likely not core clock tick-competitive, since it's a now-long-in-tooth K8-generation design.

As such, AMD is taking an unfortunately now-familiar tack with its new CPU; immediately targeting the mainstream market, versus more profitable (albeit lower shipping volume) leading-edge system configurations. And again taking a now-familiar tack, the bulk of the embargoed Puma platform presentation the company briefed me on ahead of today's unveiling was focused on graphics, both discrete and integrated within the CPU-companion core logic chipset.

Taking advantage of a multi-week push-out in the release of Intel's Montevina (aka Centrino 2) chipset (which, I agree with Peter Glaskowsky, is probably just the result of a late-discovered minor timing path-induced bug which will require testflow screening and/or clock speed reduction until a silicon stepping fixes it), whose beefed-up graphics and hardware-accelerated video processing capabilities I alluded to back at the Santa Rosa launch, AMD sees a slender but solid schedule gap in which it can make its pitch. I confess that its 3D advocacy largely falls on deaf ears as far as this particular industry observer is concerned; the bulk of leading-edge gaming is now being done on consoles, not PCs, mainstream gaming titles are authored such as to not overshoot the capabilities of the bulk of the market (i.e. Intel integrated graphics), and no other high-volume and performance-pushing 3D application has yet emerged. Though, admittedly, I do buy their claim that, all other factors including pricing being equal (a big assumption in and of itself), customers will prefer a computer whose graphics subsystem gives them a higher average frame rate and/or the ability to crank up the quality settings.

Video processing, on the other hand...now that's an entirely different story. It's already no surprise to long-time Brian's Brain readers that, whether disc- or download-delivered, two key video transitions are well underway:

• Standard- to high-definition, and
• MPEG-2 to more advanced albeit more performance-intensive codecs, such as VC-1 (i.e. WMV), H.264 (i.e. MPEG-4 AVC, MPEG-4 JVT, MPEG-4 Part 10) and On2's VP series.

AMD doesn't yet hardware-accelerate On2, but it does a substantial job of offloading the CPU from MPEG-2, H.264 and VC-1 decoding tasks (which is a particularly big deal in a battery-operated system configurations), as well as de-blocking, noise-suppressing and otherwise enhancing the per-frame image quality. And, although the AMD spokesperson I spoke with was unable to discuss any GPU-based video encoding acceleration support plans, the graphics cores' shader-based architecture makes such capabilities highly likely in the future.

Puma's Wi-Fi capabilities, at least for now, continue to come from third-party partners versus from AMD itself. In the midst of the AMD spokesperson's vigorous advocacy of the competence of suppliers such as Atheros, Broadcom, Metalink and Ralink in this regard, as well as the benefits to AMD's customers of this sourcing flexibility, I interrupted him with the following observation:

This is the same thing you were saying two years ago about graphics, before you bought ATI. What's so different this time, to lead me to believe you won't soon buy a Wi-Fi silicon supplier, too?

The spokesperson him-hawed and basically avoided answering the question, at the same time pointing out that Nvidia was a valued Puma platform partner from a discrete graphics add-on standpoint (yeah, right). My take?

1. AMD is in such a fiscal hole right now that it doesn't have the cash to do another acquisition, even if it wanted to,
2. The company has little-to-no expertise in the necessary analog areas to implement a robust wireless PHY, and anyway
3. The Wi-Fi PHY is fundamentally incompatible with a high volume, low cost digital CMOS process, from a single-die integration standpoint, which is where AMD is headed.

What's your take on AMD's Puma platform, and its chances?