Brian's Brain

Continued from 'Solid-State Storage: Portending Supply And Demand'...

Multi-level cell flash memory, which stores two bits of information within each array transistor, would seem at first glance to be an ideal means for a flash memory supplier to maximize its fabrication facility output. Although MLC technology does roughly double the amount of storage capacity associated with a given-sized piece of silicon as compared to SLC (single-level cell) flash memory, other important MLC-versus-SLC tradeoffs also bear consideration. MLC flash memory read speeds are slower than SLC specifications, a reflection of the more precise algorithm required to sense the amount of charge stored in the MLC transistor's floating gate, but this factor is somewhat mitigated by the fact that each read cycle outputs two bits' worth of data in the MLC case versus one bit per cycle with SLC.

Write cycles also take significantly longer with MLC as compared to SLC, due to the need for more precise charge deposition on the floating gate. A MLC flash memory's cycling specification (the number of times you can erase a block while still remaining within the device's maximum program and erase time specifications) is notably lower than that of a SLC alternative. Even in the absence of cycling, MLC flash memory storage transistors have an inherently higher susceptibility to charge disturb phenomenon caused by alteration of nearby transistors' stored information. Fortunately, a combination of careful design and infant mortality test screening done by the vendor prior to shipping product to you should weed out charge disturb tribulations.

Some words on cycling close out this particular addendum. As earlier stated, it's highly unlikely that a storage transistor will flat-out fail when it reaches its maximum cycle count threshold; it'll just take longer than specified to program and erase. Well-understood (by now, two decades into the flash memory revolution) foreground- and background-operating media management algorithms eliminate cycling 'hot spots' within the array, thereby significantly pushing out the point in time when any one block reaches the maximum cycle count specification. And spare block allocation at the beginning of a system's life enables subsequent block retirement-and-replacement techniques later in life that further prolong the operation of a flash memory-based mass storage peripheral.

To this point, you could potentially construe that a SSD is more reliable than a HDD. By data-logging per-block cycle counts and program-and-erase time trends, your system can predict (and circumvent) a given block's ultimate failure point far in advance of its actual occurrence. SSDs therefore have a substantially lower probability of 'hard' failure as compared to, for example, the read/write head 'slap' of a HDD's platter or the breakdown of its motor.