Advertisement

Zibb

Brian DipertEDN Senior Technical Editor Brian Dipert exposes, analyzes and
opines on diverse topics in technology. Follow the Brian's Brain Twitter feed at www.twitter.com/BrianzBrain.



   Advertisement

Profile

RSS Feed

  • Add this blog to your RSS newsreader!

Recent Posts

Recent Comments

Most Commented On

Archives

By Category

Consumer Electronics Design Articles

Blog

Wednesday, December 17, 2008

An x86 Wednesday: AMD's 65nm Distress And An Intel Naming Contest

Dec 17 2008 10:26AM | Permalink |Comments (24) |


AMD, a company which (along with its competitors) I've criticized in the past for conducting intros that were heavy on hype and light on significance ("lots of sizzle, little steak", as the saying goes) notably shifted gears on Monday when it rolled out the Athlon X2 7750 Black Edition and Athlon X2 7550 dual-core CPUs. The company was so quiet that it didn't even generate a press release to commemorate the occasion; see for yourself. At first, I was baffled, because although the products' names imply an extension of the longstanding K8 microarchitecture, they're actually the company's first dual-core products derived from the K10 'family tree' that previously spawned Barcelona (i.e. the quad-core Opteron) and the triple- and quad-core Phenom. But once I dug into the details, the likely reason for AMD's reticence become more clear.

The 2.7 GHz Athlon X2 7750 Black Edition, complete with an eyebrow-raising $79 1,000-unit price tag, is the only chip of the two that will be sold directly to consumers; as its name implies, it has an 'unlocked' core clock that's amenable to overclocking and other technical shenanigans. The OEM-only Athlon X2 7550 (with unpublished pricing) runs at 2.5 GHz. Both chips offer 2 MBytes of L3 cache, the same memory allocation as their triple- and quad-core Phenom siblings, which was my first clue that these weren't dedicated dual-core IC designs (which AMD's original 'Kuma' roadmaps had suggested would be the case). And, as it turns out, their 283mm2 die sizes are identical to 65 nm Phenom CPUs...these chips are in actuality quad-core Phenoms with two on-die CPU cores disabled.

I was admittedly flabbergasted when AMD rolled out its single-core-disabled Phenom products, after considering the amount of silicon the company was leaving unused (therefore non-revenue-generating), and thereby interpreting how poor the company's 65 nm fully-functional die yields must be. Now I frankly don't know what to think. Take a look at a Phenom die shot and you'll see just how much area each core and its corresponding L1 and L2 cache allocation takes up:

Eyeballing this image, I'm guessing AMD's wasting at least 33% of each dual-core CPU's surface area. Have 65 nm yields plummeted even further? Does AMD have so much unsold 65 nm product in inventory that it's doing a fire sale to clear out the warehouse? Or have the company's aging K8-based dual-core products just become so uncompetitive that AMD was forced to make this desperation move? Regardless, as I said just last week, 45 nm-based Phenom II can't come soon enough...and the company had better hope that this particular lithography and products based on it are much more robust than their troubled predecessors.

AMD's troubles don't exist in a competitive vacuum, of course, there's Intel's imposing Nehalem microarchitecture to consider. The first products derived from the Nehalem foundation are Intel's Core i7 chips, whose naming is among the most bizarre the company's marketeers have ever come up with (to the limits of my admittedly imperfect memory). Intel's PR folks assure me that 'all will be clear' when future Nehalem variants also appear, but in advance I think I may have already cracked the code. Core i7 chips have:

  • Four CPU cores, and
  • Three onboard memory controllers

4+3=7, i.e. 'Core i7'. It's feasible to expect that future, lower-priced Nehalem spins will make silicon-slimming (got that, AMD?) allocation reductions of one or both resources.

What, if anything, do you think 'Core i7' means, readers?


Reader Comments



at 12/17/2008 11:19:45 AM, blank said:
your an idiot the x2's die ie 6400+ has the same die size as the phenom processors



at 12/17/2008 11:53:13 AM, Brian Dipert said:
Dear blank, The Athlon 64 X2 6400+ die size was 219mm2 at introduction. It was initially fabricated on a 90 nm lithography (although it may have transitioned to 65 nm by now, which would make its die size even SMALLER). And it is NOT a K10 microarchitecture-derived product. Who's the idiot?



at 12/17/2008 1:56:08 PM, Arc said:
The i7 in Core i7 is a marketing name and nothing more. Think BMW.



at 12/17/2008 2:08:54 PM, M said:
They used 'i' because everything 'i' is cool (to some people). They were going to use 8 instead of 7 (for 2008) but the floating point bug somehow got them again! I'm not sure what they needed to divide, but after they saw i7 they liked it and realized that i8 made them hungry so they left it and went to lunch. That's marketing for you....



at 12/17/2008 2:12:47 PM, Brian Dipert said:
Dear M, My head hurts...;-) Thanks for writing!



at 12/17/2008 2:42:12 PM, AMDude said:
The new X2 processors have 2 cores disabled because those 2 cores apparently did not operate properly. If they didn''t sell them as X2s then they would have to grind them up and use them for sand paper grit or something like that. AMD designs their CPUs so that any number of cores can be disabled making a disfunctional die into a working die. Yeah, they may be not using 33% of the die, but if they didn't disable those 2 cores they would be wasting 100% of the die.

Understand now?



at 12/17/2008 2:48:56 PM, Jack said:
Do they sell one-core and 3-core products too?



at 12/17/2008 3:28:21 PM, phileasfogg said:
AMDdude -- wow, such coruscating brilliance. Are you sure you're not somehow connected to the Hope Diamond?

Dripping sarcastic,
Phil



at 12/17/2008 3:53:12 PM, AMDude said:
Jack - They sell X4, X3 and X2. All using the same die. Haven't seen any hint of an X1, hey gotta get sand paper somewhere!

Phil - Thanks for the compliment....NOT. Anyway, I wouldn't even have bothered to post except Brian's Brain obviously needed the info. Didn't figure anyone else did.



at 12/17/2008 4:00:27 PM, Brian Dipert said:
Dear AMDude, you stated the intuitively obvious. So let me toss this seemingly intuitively obvious hint back at you, since you apparently need the info; AMD would much prefer to sell those chips as fully-functional four-core die, considering that it incurs package, test, inventory and distribution costs regardless of whether they turn into two-, three- or four-core products (with incrementally higher corresponding two-, three- or four-core price tags). As I said before, the company's apparently got serious 65nm manufacturing problems, or a glut of 65 nm products sitting in warehouse and in-line in fab, or is no longer competitive with dual-core K8 so has been forced to sell quad-core K10 as dual-core K10...or some combination thereof.



at 12/17/2008 4:48:27 PM, DM said:
Brian, you need to know relative part volumes to deduce manufacturing problems. With a simplistic yield analysis, if the 4-core chip has 80% yield (good), there will be 16% 3-core chips and 3% 2-core chips. At high enough volumes, these are worth selling.




at 12/17/2008 4:52:37 PM, AMDude said:
Gees, do ya think? How remedial. Creating 4 core processors to sell as 4 core processors. Of course they want to sell them as X4s! But if their NOT fully functioning X4s, should they be tossed? Of course not.
Here''s another news flash for ya, the K8 X2 hasn''t been competitive since Intel introduced the Core2s to the desktop! AMD has been trailing for about 2 yrs now. But now the K10 and K10.5 architecture is coming along and they''re doing the same thing they did with K8... any X4s with disfunctional cores are downgraded to X3s or now, X2s and sold for what they will bring. FORCED to sell the K10 X4s as X2s? Come on man, that''s a stretch! Why not just deeply discounted X4s? Oh yeah, that''s what they''re doing already.
How about some more intuitively obvious info for you. AMD has never had serious manufacturing problem with their mature processes. The only manufacturing problems they had is lack of capacity and lack of funding. Whether or not they have helped that with their recent endeavors remains to be seen. Their yields have traditionally been extremely good as their processes mature. Far better than the other guys in some instances.
Your assumption that selling defective X4s as X2s denotes yield problems is based on nothing more than that..... an assumption.



at 12/17/2008 6:21:57 PM, Brian Dipert said:
Dear AMDude, No, it doesn't always make sense to sell partially-functional die (otherwise more companies would do so). By turning them into two- or three-core CPUs, you incur incremental packaging, packaged unit test, warehouse, and transport costs...costs that you wouldn't incur if you just toss them, and that must be counterbalanced against the price you would be able to charge for them. It only really makes sense if your fully-functional yield loss is very high (as DM rightly suggests in his comment)...a function of large die sizes, process excursions, etc. Leading me back to my fundamental point...which, I might add, is only one of three possible (and potentially intertwined) scenarios explaining why AMD decided to go this route.



at 12/17/2008 6:25:12 PM, Brian Dipert said:
Dear DM, a valid point. But in a 'perfect world' with sufficient design resources at your disposal, wouldn't it be far preferable to do a dedicated dual-core layout? So yes, in part this reflects all the layoffs AMD has done of late, as well as its fundamentally smaller employee headcount as compared to Intel. Thereby making Barcelona, which I suspect consumed a large percentage of that headcount, look like even more of an albatross in retrospect. Intel had its albatross too in Itanium, but the company's much larger size meant that Itanic didn't have near the same negative impact.



at 12/17/2008 6:40:45 PM, phileasfogg said:
AMDude - sorry, I didn't mean to offend you. Your points are all valid.

Brian-- I'm surprised no one has yet mentioned that this "die recovery" strategy has been used extensively in the GPU market. It is common knowledge that nVidia uses the same multi-core "die" and sells GPUs with a smaller number of 'working shader cores' at lower price points. It's a very smart approach, but like you said, there is some extra work to be done.

a) the wafer sort program must add more "bins" for partially good die and identify them as such.

b) during packaging, there must be a way to identify these 'fractionally good' GPU parts (easy to do with ID resistors on the substrate) so that the package-test program on the tester only tests for the 'good' cores.

This approach is almost entirely a 'bottom line' adder. Yes, like you said, there are packaging and final-test costs, but when the ASP is > $10-15, these 'backend' costs are dwarfed by the ASP recovered. And best of all, the bean-counters in the accounting/finance department would be drooling all over their Lands End oxfords when they see incremental dollars flowing straight to the bottom-line ;-)

-- Phil




at 12/17/2008 7:01:54 PM, Brian Dipert said:
Dear phileasfogg, I realize that (I also cover GPUs). And pragmatically, as die sizes increase and as lithographies shrink (therefore the likelihood of particulate-induced failures increases) AMD's design-for-partial-functionality approach may become more prevalent. Intel, after all, has followed a conceptually similar path...disabling coprocessors to sell 486DX die as 486SXs, disabling part of the cache to sell Pentium die as Celerons, etc. But this has always been a TEMPORARY move on Intel's part; eventually, as volumes ramp, they do a dedicated silicon area-optimized die layout of the end product. As I pointed out to DM, this situation is as much a reflection of AMD's engineering resource limitations as it is anything else. And considering it's been over a year since Phenom launched, it's a particularly unfortunate situation.



at 12/17/2008 7:14:16 PM, AMDude said:
Phil - No problem dude.

BB - Last time I promise. I can't see costs really being an issue because all of the dies are already being tested for functionality already, packing and shipping of the X4s is already taking place so whats a few more of the X3s and X2s. Lastly, warehousing? This is MAD man, they can't supply the customers they have fast enough, I'd be surprised if they had much warehousing space AT ALL. And DM DID NOT suggest that their vield loss was high, he said 80%! Intel would be giddy if they could get 80% yield! Anyway, we will have to just agree to disagree. Until next time...



at 12/17/2008 8:09:32 PM, RoboCop said:
I am not suprised to hear of AMD's yield woes. As someone who has worked on AMD's microcontamination issues in Dresden, Germany, I often came up against the German "we are better than you" attitude. We could have helped them, but unfortunately the girl that leads the efforts couldn't negotiate her way out of a paper bag....



at 12/18/2008 9:28:31 AM, Zilda said:
All this makes me wonder about AMD's long term survivability - I came across this and thought it was an interesting question. Would be interested in others' thoughts

home.inklingmarkets.com/stocks/54066/trades/new



at 12/18/2008 10:32:14 AM, DM said:
One point that has not been mentioned in this discussion is that at smaller geometries, it becomes increasingly difficult to have all cores running at the same clock frequency. So the future will be parts sold at average core performance, rather than guaranteeing all cores run at a minimum frequency. Today this means some downbinning, counteracted by some supply voltage programming. But depending on pricing, it can make sense today to sell a chip as 2 or 3 cores, with those cores at high clock frequency, than to sell it as a 4-core chip at a lower clock frequency.

Regarding the test costs, there is relatively little increase in test time or cost to support this strategy. The number of bins does not increase, since the split between 2, 3 and 4 core product can be done at wafer test with an electronic wafer map, and once packaged, these parts can be treated as different part types, headed for burn-in and final speed binning. As was noted above, for microprocessor products, it pays off if the volume is high enough. One issue is that the large customers for the 2-core parts are probably the large customers for the 4-core parts, so if your yield goes up too much, you may have more demand for 2-core products than you have supply, so you might have to sell 4-core chips as 2-core chips. It happens.




at 12/18/2008 12:02:23 PM, BobsUrDad said:
Does OEM parts mean "NO WARRANTEE" ? I wouldn''t touch these parts with a ten foot pole. Seems like they''re dumping bad parts on the market and hoping some suckers will pick them up.

If they don''t have the confidence to put it in a retail box with quarantee -- stay away.



at 12/18/2008 12:24:26 PM, Brian Dipert said:
Dear BobsUrDad, No, OEM only means parts sold directly to companies like Dell and HP (ie 'OEMs') for inclusion in their PCs, versus parts sold directly to consumers at retail for homebuilt PCs and upgrades...



at 12/18/2008 3:26:48 PM, Deron Freed said:
at $79 per CPU, this is give Pentium and Core 2 duo a good run for their money.

America likes underdog.

GO AMD.



at 12/22/2008 3:35:17 PM, Scunnerous said:
I don''''t see what the big deal is here - surely it''''s perfectly obvious that with multi-cores, we simply have a new angle on binning: if two out of four cores will only run at say 2.2GHz and the other two can run at 2.7Ghz, what would you have them do?

Perhaps one should find out what Intel does with such chips, or would they have us believe that theirs are all symmetrically perfect specimens? Of course we''''d have to believe them - no?Ô_õ


Post a comment



Display Name

Change Image
Before submitting this form, please type the characters displayed above.
Note the letters are NOT case sensitive.


ADVERTISEMENT

©1997-2010 Reed Business Information, a division of Reed Elsevier Inc. All rights reserved.
Use of this Web site is subject to its Terms of Use | Privacy Policy