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Friday, October 3, 2008

More Transistors For Lower Power Consumption, More Transistors For Higher Performance: Analog Devices' Latest DSPs

Oct 3 2008 12:00AM | Permalink | Email this | Comments (1) |
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Question: An engineer's at the beach. In scanning the ocean, (s)he sees a large dorsal fin poking out of the waves, and heading at high speed straight for a group of humans near shore. What does (s)he shout?

Answer: SHARC!

Ahem. Greetings from the 125th Audio Engineering Society Convention in San Francisco, and apologies for the lame attempt at humour; I tend to get a bit loopy when I travel ;-) I take full responsibility for the preceding (bad) pun; Analog Devices was in no way, shape or form involved in its fabrication.

Speaking of fabrication...and of Analog Devices...in this modern era of mainstream 65 nm processes, leading edge 45 nm-based products from tier-1 silicon suppliers and foundries, and coming-soon next-generation lithographies, ADI's 130 nm SHARC products were beginning to look a little long in the tooth. Their longstanding performance leadership (at their targeted price points) was starting to run out of steam. And perhaps just as important, their amount of on-chip memory was getting increasingly squeezed by burgeoning function-driven software growth, combined with the industry shift away from space-efficient assembly code towards schedule-efficient high-level languages such as C.

As such, ADI's latest-generation ADSP-214xx SHARC DSPs make a two-full-generation lithography leap down to 65 nm, bypassing the leakage current-plagued 90 nm node in the process. Predictably, the company uses the bulk of the substantial incremental transistor budget afforded by the process migration to beef up the amount of on-chip code RAM...to 5 Mbits (67% more than that offered by the largest 213xx predecessor).

To further improve memory utilization, while 214xx SHARC DSPs are backwards code-compatible with software created with prior-generation SHARCs, you can optionally compile your going-forward code with enabled support for variable instruction sizes, whose average compression capability ranges from 20-30% according to company officials. And if you're still running out of onboard RAM, you can supplement it with off-chip memory resources; Analog Devices has upgraded the integrated memory controller to DDR2, running at speeds up to half the core clock rate, in order to keep pace with the currently most available/lowest cost-per-bit SDRAM flavour. You can now even now DMA data between the serial ports and external memory.

A more modern lithography foundation also translates to higher clock speeds; the ADSP-21469 (the high end audio-tailored first member of this SHARC family, unsurprisingly unveiled here at the show, where SHARC has long been a bastion in the pro audio hardware ranks) runs at up to 450 MHz. While that much speed might at first glance seem sufficient for nearly any application you could imagine, company officials assure me that the converse is often the case, thereby justifying the dedicated FIR, IIR and FFT transform engines that the ADSP-21469's transistor budget also afforded:

The resultant cumulative peak processing 'muscle' of the ADSP-21469 is estimated to be 2700 MFLOPS. This excerpt from a white paper (PDF) authored by DSP Concepts' Paul Beckmann further fleshes out the transform function blocks' justification:

Application software must be designed to get the most out of the hardware accelerators. Keep in mind that the accelerators must be configured to operate in parallel with the main CPU, because there is no benefit if the main CPU is idle waiting for the accelerators to finish. The accelerators are typically part of a larger signal chain running within a real-time environment. Interfacing to the accelerators requires double-buffered input and output data, and the system designer should bear in mind that the accelerators introduce a block of latency.

Consider a home theater system with 7.1 channels of audio at 96 kHz operating at a block size of 32 samples. Assume that room equalization is being applied by eight FIR filters, each 512 points long. If the core CPU were to perform the filtering, it would take at least 96 kHz x 8 x 512 = 393 MMAC/second or 44 percent of a 450 MHz SHARC processor. This FIR processing represents a significant portion of the overall computation, and fortunately, can be offloaded to the accelerator. The inputs and outputs to the FIR filters are double buffered allowing the accelerator to operate in parallel with the rest of the audio signal chain. The double buffering introduces 32 [samples] of delay in the processing, which is an acceptable 333 microseconds at 96 kHz.

Using the previous formula, the accelerator requires 50,056 peripheral cycles to complete the operation. At a rate of 225 MHz this is 223 microseconds, which is well within the 333 microsecond block time.

And here's the overall ADSP-21469 block diagram, for your in-depth perusal:

One other feature (of the many) of the ADSP-21469 bears specific mention. In my briefing with the company last week, I asked about the status of the multi-core TigerSHARC product line. ADI's spokespersons, while assuring me that existing products (and system designs based on them) would continue to be fully supported, indicated that I shouldn't expect to see further product proliferations in the future. Alternatively, ADI has re-included the 8-bit link ports (two on the ADSP-21469) absent on the ADSP-2136x series, for inter-processor communications purposes:

How will standalone DSPs such as SHARC stack up against CPU-integrated alternatives like Blackfin in the long term, especially if Moore's Law trends result in the latter product family eventually garnering native floating point augmentation? I can't wait to find out. Nearer term, though, ADSP-21469 design efforts have wrapped up (the chip has 'taped out', for those of you familiar with semiconductor vernacular), and assuming that first silicon comes back from fab, packaging and test in solid (enough) shape, initial customer sampling is scheduled for January. The ADSP-21469 will cost $31.50 in 1,000-unit production quantities.

How will ADI fill out the ADSP-214xx family, and how will competitors such as Cirrus Logic, Freescale and Texas Instruments respond? Again, I can't wait to find out; file your predictions in the comments.


Reader Comments


at 10/5/2008 9:38:46 AM, robert@analog said:
Brian: I also like the "long in the tooth pun". I think there will still be a place for high performance floating point DSPs over the long term. As long as algorithm designers keep reaching out for the next best form of sound processing, advances like these will be needed. I see a long life for SHARC, long live SHARC. Rob@analog_devices

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