The Sandbox

According to Applied Materials, it is.

As 32 nm technologies ramp within the next two years, the extension of optical lithography to meet patterning requirements is the industry’s most urgent technology hurdle, the company reminded.

Applied recently held technical discussions and presentations on the self-aligned double patterning (SADP) technique that it proposes may be the most cost-effective answer to continued scaling down to the 22 nm node, whereby a consensus was reached that extreme ultraviolet (EUV) lithography will eventually replace optical lithography, but since EUV is not likely to be ready for mass production until 2012, optical lithography must pattern 32nm and possibly even 22nm devices.

While immersion optical lithography has found acceptance and many companies are planning to use it at the 45 nm node, beyond 45 nm more advanced immersion fluids and lenses are necessary, but those developments are not expected to be ready for the 32nm node.

Enter double patterning (DP), a technique that prints the pattern in two steps to double the pattern density.

The two main approaches to DP are double exposure (DEDP), which uses two masks, and self-aligned double patterning (SADP) (also known as spacer-based patterning), which generates pairs of features from a single parent, Applied also said.

In the case of DEDP, the most difficult challenge is overlay control, and the exact overlay specification is a matter for debate, but Dr. Cheol Bok of Hynix explained during Applied’s panel discussion, that it must be as low as 1 nm, much lower than the 5 nm being currently demonstrated. This specification gap may prove difficult to close in time for 32 nm.

In terms of SADP, one of the key advantages is that because all features come from a single exposure, the overlay error is greatly reduced. Applied’s Anisul Khan said the company’s advanced patterning films allow very low line-edge roughness and are tolerant of photoresist imperfections, which often improves CD uniformity as the pattern is transferred into the underlying layers.

Also, Chris Bencher, from Applied’s Maydan Technology Center, showed 32 and 22 nm demonstration results in APF hardmask, TANOS, Cu-filled trench, oxide, STI and logic structures, which demonstrates the production-worthiness of SADP, during a presentation, noting that at least one major memory manufacturer is using SADP in 45 nm NAND flash memory production today.

Further, while SADP may be appropriate for regularly structured memory devices, it may also be able to be extended to logic, according to Milind Weling from Cadence Design Systems during the panel, who explained that it is entirely feasible to alter the design rules for logic to produce flash-like structures, and demonstrated layout tools for automating the process. Tela Innovations recently announced tools to redraw existing logic layouts to follow “gridded” design rules, while Applied has validated this approach by fabricating demonstration logic structures using SADP.

In the end, the extra complexity of DP carries the risk of increased cost, and the industry is now trying to determine how these costs can be offset and actually reduce the cost-per-chip, which is the most important metric.

Applied believes the answer lies in increased productivity in every area: denser features results in more chips per wafer; improvements in defect control, such as the introduction of “bevel engineering” will reduce defectivity and boost the number of good chips; and new factory automation software tools to increase output by raising overall fab productivity.

With this in mind and with more data becoming available on double patterning, what are your thoughts as to the cost-effectiveness of double patterning?