FPGA Gurus

Mary-Jo Foley’s blog, “All Things Microsoft,” has an ongoing feature on Microsoft’s “Big Brains.” This week, she interviewed Chuck Thacker, winner of the 2007 IEEE Von Neumann medal, on the use of FPGAs as a development vehicle for new operating system concepts. Thacker has helped develop the Berkeley Emulation Engine v3, or BEE3, as part of the Research Accelerator for Multiple Processors (RAMP) project.

Efficient use of dozens of cores is of paramount importance in thread development for next-generation operating systems, but the BEE3 project could have important implications for hardware development as well. Even system developers using multiple cores in standard Intel, Sparc, or other RISC architectures worry about the drop in efficiency in moving to four-way processing and beyond. The move to multiple-core implementation in an FPGA can benefit from academic projects like RAMP, which utilize multiple physical FPGAs to emulate multicore single-chip architectures.  In fact, RAMP has launched a new RAMP Gold project, utilizing two separate emulation systems based on the Xilinx Virtex-5, to experiment with multicore implementations of the Sparc instruction set - intriguing, given that Intel was a co-sponsor with Microsoft of the Parallel Computing Lab working on RAMP Gold.

In the heyday of RISC architecture development, system designers could benefit from the vertical profiles offered by coalitions like Power.org and Sparc International. But in periods of economic retrenchment, designers in private industry recognize anew that research projects from academia can fill important gaps as corporate research projects falter. It’s also interesting to see how a software giant like Microsoft can provide practical help to the FPGA community on algorithm and application development.