FPGA Gurus

GateRocket Inc. announced this week the expansion of its verification accelerator, RocketDrive, from an original base in Xilinx Inc.’s Virtex-5, to the Altera Corp. Stratix IV. GateRocket will be showing off this disk-drive-sized device for accelerating HDL simulation at the upcoming DVCon in San Jose.

The miniaturization of hardware simulation tools led me to think about a decade’s worth of Moore’s Law, FPGA complexity advancement, and the evolution of hardware emulation and simulation tools, using FPGAs as both enablers and targets. It was almost exactly ten years ago, after all, when Cadence Design Systems Inc. completed its acquisition of Quickturn Design Systems Inc.

In those mystical days of yore, banks of FPGAs were used in large platforms the size of test-equipment or server platforms, all intended to emulate the functionality of a single advanced VLSI processor or ASSP. In that long-forgotten era, after all, FPGAs only were large enough to take over MSI or small gate array duties. As the system-level Quickturn emulation tools were absorbed into the Cadence suite, hardware functionality similarly was absorbed and reduced in footprint until it reached board level (where vendors like Dini and Hardi could offer pre-configured boards). The emulation function for all but the largest ASIC designs eventually “disappeared through the skylight.”

Meanwhile, FPGAs became large enough to themselves take on the functions of processors and ASSPs, and to serve as verification tools for implementing functions in their own architectures. The Von Kekule dream of a snake eating its own tail is an appropriate metaphor here. And the new world of hardware verification is exemplified by the likes of GateRocket.

The intent of a PC-resident product like RocketDrive is to augment design tools from the FPGA vendors themselves, as well as external EDA tools from Cadence, Mentor Graphics, Synopsys, and Synplicity, theoretically accelerating hardware debugging processes several times or even exponentially over a software-only solution.

The Achilles Heel of the hardware acceleration approach is to identify correctly the source of an error in a design implemented in an FPGA. By offering “native fabrics” based on the leading Xilinx and Altera designs (which GateRocket calls “DeviceNative verification”), the RocketDrive tool can ease the verification task. It will behoove the company to move at a later date to Actel and Lattice architectures, and any others that survive the brutal 2009 shakeout.