Leibson's Law

Alex Mericas’ Hot Chips presentation delivered some insights into low-power processor design that IBM has gleaned from designing it’s series of server-class microprocessors: Power4, Power5, and Power6. These insights aren’t new. People involved in processor design know these tricks. But perhaps they’re more solid with IBM’s weight behind them.

Here are the basic concepts Mericas espoused:

• Turn off the clock when not needed. This technique uses a few extra gates but has no other liabilities and many positives. The Power4 processor had almost no clock gating. The Power5 processor had clock gating. The Power6 processor has “aggressive” clock gating. Must be good stuff.
• Use predictive power gating to switch off unused circuits. Note that this technique can cause some real timing problems when tryi

Sam Williams, a PhD student working under UC Berkeley’s Professor and Processor Guru Dave Patterson, gave a polished Hot Chips talk on a metric that allows undergrads (and, in my mind, overly busy design engineers) to determine when they’ve sufficiently optimized software to run on multicore parallel processors. Note that this model is about optimization, not writing correct parallel programs. "If you can't write a correct parallel program," said Williams, "you shouldn't be worried about optimizing it." 

William's concept is called the “Roofline Model” and I thought about summarizing it here, but I’d need a blog entry the length of the presentation to do it. So go get a copy yourself on Williams’ Web page.

Essentially, the Roofline model tries to pair inform...Read More

Here’s a crazy idea: extend memory coherency for an SMP system across a LAN. Now why in the world would you do something so crazy? Well, it turns out that servers have a lot of trouble distributing loads and allocating resources. The result is low server utilization. SMP systems partially solve this problem by creating a pool of processors linked by coherent memory. Any processor can restart any stalled task because of the coherent memory. However, the number of processors in a cluster is limited and processors in other SMP clusters located in other parts of a server farm at the other end of LAN piping do not have a coherent-memory link so they cannot be easily used for load distribution without a lot of data movement across the LAN. That’s super slow.

So, the answer is simple. Just extend memory coherency across the LAN. That’s the solution that ...Read More

Monday was the day of the multicores at two Bay-area conferences. Early in the morning, I drove to Stanford University’s Memorial Hall to attend Hot Chips 2008, the 20^th annual conference for leading-edge silicon. I’ll be reviewing some of the presentations in future blog entries, but for now the opening remarks of conference chair Don Draper are top-of-mind for me. Draper, whose day job is engineering manager at Rambus, opened the conference by noting that fully three-quarters of the chips to be discussed at Hot Chips 2008 are multicore designs. Further, said Draper, the largest chip to be discussed had 244 processor cores and the runner up had 167 processor cores. He then invited attendees to start planning on topping that record next year. It was a thrill to attend a Hot Chips conference where the focus was no longer “¿Quien tienes mas GHz?&r...Read More

We knew it! We knew it! We knew it! Star Trek’s been right all along!

FTL (faster-than-light) space travel isn’t impossible. It doesn’t violate Einstein’s Theory of Relativity if you sneakily distort space using dark-energy manipulation. See here.

Warm up the matter/antimatter mixture and align the dilithium crystals, Scotty! Zefram Cochrane (inventor of the warp drive) here we come.

All we need to do is convert Jupiter’s entire mass into pure energy.

Oh. I guess we’ll have to wait for the low-power version.

Less than 24 hours left before this Webinar starts. Sign up NOW!!!

Looking for a little clarity with respect to multicore SOC design? I’ll be supplying my own flavor of clarity with respect to symmetric and asymmetric multiprocessors (SMP and AMP) with a free EDN-hosted Webinar on Thursday, August 21. No hard sales pitch or marketing BS. Just technical details laser-focused on the needs of the designer.

And, did I mention clarity? (Register here.)

I just read Jack Ganssle’s column “Misguided” on his recent GPS woes. Today’s my first day at work after a week and a half car trip of nearly 2000 miles, heavily relying on my V7 NAV730 GPS unit. It was invaluable, but not infallible, so I have written my own blog entry on GPS. (Note: I’ve written about my GPS unit before: NAV730 GPS is my Copilot.)

First, the good:

1. The GPS nearly always was right. It took us to places we’d never have found with a map. It did so efficiently and quickly, when it worked.

2. Together with the Internet, we boldly went to restaurants in stran...Read More

HP introduced its first inkjet printer, the ThinkJet, in 1984. No one mistook it for a high-quality printer. It competed with 9-wire impact dot-matrix printers (primarily from Epson) at the time. However, HP’s marketing and engineering teams recognized the vacant market niche for a “low-cost” printer (defined as under $1000 at the time) that could deliver laser-quality printing. So HP’s DeskJet engineering team went about re-engineering the existing ThinkJet technology to boost the print resolution from 96 to 300 dpi, which required several mechanical, electrical, and electronic innovations.

You can read about these innovations, plus the straightforward approach to “real” market research (as opposed to HP&rsq...Read More

Looking for a little clarity with respect to multicore SOC design? I’ll be supplying my own flavor of clarity with respect to symmetric and asymmetric multiprocessors (SMP and AMP) with a free EDN-hosted Webinar on Thursday, August 21. No hard sales pitch or marketing BS. Just technical details laser-focused on the needs of the designer.

And, did I mention clarity? (Register here.)

Yesterday, SpaceX announced the third launch failure of its Falcon 1 orbital rocket, launched from the U.S. Army's Reagan Missile Test Site on Omelek Island in Kwajalein Atoll. Also announced yesterday was the loss of the multiple satellite payloads. Today, SpaceX announced the cause of the failure: timing error. After first and upper stage separation, the first-stage’s engine continued to run while the second-stage engine had yet to start. As a result, the rocket’s first stage bumped back into the second stage and the mission was lost.

SpaceX also reported that the launch included the ashed remains of 200 people including actor James Doohan. That would the guy who was responsible for making many of us decide to be engineers because of his role as Commander Montgomery Scott, in the original Star Trek television series.

Aye, we miss ye Scotty.

Just in case my last blog post made you think “Leibson’s got it all figured out.”—fat chance. Let me clue you in to the near future. Nothing will be like today. At 65nm, we already see enough device variability within a die to know that normal system design as we do it today is going to flat-out perish. Today, we design most digital systems on the foundation assumption that a NAND gate always works like a NAND gate. We assume 100% functional chips. If the chip isn’t perfect, we toss it. Seems wasteful but it's always worked. No more.

Sure, memory designers have long had to add redundant rows and columns to boost yield. That’s just a yield/economics thing. Sure, some designers have added parity and ECC to their memory systems because memory has long been known to have hard and soft errors. But logic? That’s always been solid. Boole ...Read More

A lot of wildly divergent things have been percolating in my mind with respect to ASIC and system design, and I’m ready to take a stab at pouring out the first cup to see how this brew looks. Here are some of the disparate elements that went into this blog entry:

• Jack Ganssle’s Develop Firmware...In Half the Time DVD
• This EDN article: Your chip in half the time? by Rajiv Maheshwary from Synopsys
• eASIC’s very recent announcement of its 45nm Nextreme2 zero-NRE ASIC
• A discussion about ASIC design that I just had with Tensilica’s Chief Architect Bill Huffman (sorry, no hype

How’s your latest firmware project going? Bugs? Schedule slipping? Resource problems? Headaches? Not sleeping well at night? Driving you to drink? Thought so. It’s the same for everyone. The usual schedule slip for embedded firmware projects is 100%. It always take twice as long as our most coldly realistic estimates. You say you’d like to escape this particular hamster wheel? Really? Honestly? OK, I can tell you how—but there’s a catch. After I tell you, most of you won’t do it. How do I know? Because you never have.

OK, OK, I’ll tell. You can escape the traps quickly and inexpensively without a lot of pain by embracing Jack Ganssle’s vision of firmware development and managing your software projects with realism and managerial backbone. Who is Jack Ganssle you ask? He’s the ...Read More

Tom Halfhill, Senior Analyst at InStat, writes for the Microprocessor Report, a newsletter dedicated to discussing new developments in microprocessors and microprocessor-based systems. Microprocessor Report is also a sister publication to EDN. Tom has just published a good editorial on Multicore Programming tools. While I can’t deliver the whole editorial to you—Microprocessor Report is a paid-circulation newsletter—I can show you some of Tom’s editorial because he’s conveniently put an excerpt of it in InStat’s free email newsletter called Processor Watch:

...Read More

Time was, back in the early 1970s, calculator chips were the ultimate proof of semiconductor manufacturing prowess. Many 4-banger (add, subtract, multiply, divide), battery-powered, handheld calculators were available. These machines were based on the biggest and best PMOS LSI chips that the IC vendors could build at the time. There were literally thousands of transistors on each chip! Imagine that.

Meanwhile, Bill Hewlett was gently beating on Tom Osborne, Dave Cochran, and the rest of the HP 9100A programmable desktop calculator team to develop a pocket-sized scientific calculator for which, according to market-research done by SRI, there was no market. The result was the HP 35, the world’s first pocket scientific calculator, which launched HP into the calculator market for a fantastic run of very profitable calculators based on custom HP-designed sil...Read More