Leibson's Law

I participated in the Japan Microprocessor Forum in Tokyo last week and listened to most of the presentations. I wanted to discuss a few here in my blog. The first presentation I want to discuss was by Belli Kuttanna, chief CPU architect in Intel’s Ultra Mobility Group. Kuttanna spoke about Intel’s new Atom x86 processor architecture, which has been engineered from the ground up for low-power operation.

The Atom architecture design team took a clean-sheet approach to the design and considered every feature and option from a performance/power perspective. Kuttanna said that features fell into three performance/power groups. One feature group gave 1% incremental performance improvement for 3% or more in power. The middle group gave 1% incremental performance improvement for a 2% increase in power. The low group gave 1% performance improvement for 1% or less in additional power. The Atom design team only added the most power-efficient features.

So what features did they add? Well, they didn’t put in out-of-order execution. “Power hungry” said Kuttanna.

In addition, the design team took a giant step backwards in time and discarded the deconstruction of x86 instructions into micro-ops. Instead, they optimized the Atom processor’s pipeline to directly execute x86 instructions. Instead, the Atom processor has a pre-decoder that parses the multi-byte x86 instruction stream and inserts end-of-instruction markers in the cached instruction stream to accelerate instruction decoding.

The design team also added SMT (simultaneous multithreading) because it delivers a performance/power payback ratio of 2x, which fits the selection criteria discussed above. However, the team stopped at two threads because the efficiency fell off with more threads.

Finally, Kuttanna discussed the many power-down states built into the Atom processor and he put up a slide showing what’s going on in each state. Looks like hieroglyphics to me, but I repeat it here for your amusement. One salient point for this image: The processor needs 90 microseconds to wake up from the deepest-sleep C6 state.

One more note: The current Atom processor is implemented in Intel’s 45nm process with the high-K halfnium transistors but Kuttanna said that Intel had not had time to exploit all of the low-power features available with this process technology. So stay tuned for x86 processors from Intel with even lower power consumption.