Steve LeibsonLeibson's Law: It takes 10 years for any disruptive technology to become pervasive in the design community. This blog is about the disruptive technologies that either have or will win over electronic engineers, some that won't, and why. Written by Steve Leibson, Tensilica's Technology Evangelist. See my history site at www.hp9825.com.

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Thursday, December 20, 2007

If Done Right, IP Reuse Delivers Big Gains for SOC Designs

Dec 20 2007 1:14PM | Permalink | Email this | Comments (5) |
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Over the years, Ron Collett has collated survey data on more than 1200 IC design projects at more than 35 semiconductor companies. His research results include reuse statistics on some 15,000 IP blocks. Collett delivered some solid conclusions based on that research at the IP 07 conference held in Grenoble earlier this month. The good news is that IP reuse indeed works and delivers enormous and quantifiable benefit.

No one knows more about managing large chip-design projects than Collett. Currently President and CEO of Numetrics Management Systems, Collett spent several years at Dataquest where he oversaw EDA, ASIC, and FPGA research. He founded the research and consulting firm Collett International in 1992, which specialized in developing strategies for semiconductor and EDA companies.

Over the past 10 years, according to Collett’s research, companies have more than doubled their reuse of IP. Some of the many positive, documented results from this increase in reuse are:

  • A linear reduction in project effort (measured in person-weeks)
  • A linear reduction in project duration (resulting in faster time to market)
  • A linear reduction in the number of silicon spins needed to obtain a functional design
  • A linear reduction in schedule slip (measured as a percentage of overall schedule time)

These IP reuse benefits have accrued despite an exponential increase in IC complexity (thank you, Moore’s Law). However, the benefits didn’t come for free. Team sizes have doubled, just since the year 2000 and 85% of all IC design projects still slip their schedules. One continuing problem is that not all blocks are equally reusable. I asked Collett to tell me the most reusable type of IP block. “Memory” was his immediate reply.

IP blocks like memory are essentially 100% reusable. There’s tremendous design productivity to be gained by using such blocks. Other blocks cannot be fully reused for a variety of reasons. Perhaps the function isn’t exactly right for a new design and the block must be altered accordingly. Perhaps the block lacks adequate documentation and its functional specifications must be recovered through reverse engineering before reuse is possible.

During my discussion with Collett, I posited that most microprocessor IP also falls into the highly reusable category. Surprisingly, Collett questioned my premise. I replied that microprocessor cores are easily reused because they’re some of the most well-documented IP cores available. There are usually big, fat ISA (instruction set architecture), user, hardware designer, and programmer manuals plus sample code, application notes, software tools (compiler, assembler, linker, debugger, instruction-set simulator), synthesis scripts, and simulation models that accompany the microprocessor core’s hardware block. In addition, a microprocessor’s function can be changed through firmware, without altering the hardware IP.

A moment’s thought about those points and Collett agreed. (Hey, with my EDN, Microprocessor Report, and Tensilica background, I just had to ask. I’ve got a microprocessor-centric brain.) Collett’s thesis is that unless the IP block can be fully or nearly fully resused, the benefits of reuse don’t kick in and the benefit function is highly nonlinear. So why is Collett on this particular IP-reuse soap box? Numetrics, helps companies manage IC-design project risk and ride herd on project schedules through consulting and by offering software that gives project managers access to the industry norms derived from the company’s large project-history database. Managers can see if their proposed project schedule, productivity, and staffing estimates are in line with industry norms or if their schedules are irrationally exuberant.

For example, if the projected schedule requires the design team to be three times more productive than industry norms, it may be overly optimistic. However, if the team consists of a battle-hardened group of rocket scientists, the schedule might be realistic. Even if the design team doesn’t consist solely of superstars, a plan to push IP reuse to the max might still bring the schedule into a more realistic realm. Numetrics also provides consulting along these lines.


Related entries in: Design Strategies | EDA | Microprocessors | SOC | 


Reader Comments


at 12/20/2007 2:10:51 PM, Mordon Goore said:
Quantifiable? Linear reduction? Linear by what? Seriously, this sounds like a lot of malarkey. What does reusing an IP block buy you? 1) design time for that block 2) unit-level verification time for that block, 3) software devel time for functions that use that block, 4) unit-level synthesis, timing closure, drc, etc and 5) there is no 5. That's it. And you only get those advantages if you don't change the block at all. Touch that thing, add a function, make a minor change, at it's all over. Also because each new chip is a new assembly of blocks (some reused and others not), you still have to do all your top-level and system-level closure and verification. So, I don't know what the heck "linear" savings is, but if 3/4 of your _calendar_ time is spent on system level stuff (which cannot be done in parallel, as can unit-level efforts), then re-use at best can cut your program down 25% -- if you do it _perfectly_. Also, as an aside, I take issue with the notion that systems have had exponential scaling in complexity. Memory is a perfect example. A 1Gb array has *no* more complexity than a 1kB array. It's got more columns, more rows, and more cells, but that's not complexity, it's just transistors. Transistor counts have grown exponentially, but complexity by any reasonable definition has grown a lot more slowly. I'd say something more akin to log(engineers*design_hours*eda_improvement)

at 12/21/2007 3:44:13 AM, Philippe (D&R) said:
In case you missed Ron's talk, it is available on demand at www.us.design-reuse.com/exclusive/numetrics

at 12/21/2007 8:50:33 AM, Grant Martin said:
This is a response to the comment by Mordon Goore. If you had a project in which 75% of the time was spent on system level integration issues, and only 25% of the effort or elapsed time was spent on block design, and you had no IP reuse in this project, then I would hazard to suggest that your 75% is partly the result of a poor job on the 25% of new block design. And that if you chose appropriate IP where possible, you would see a reduction in system level integration efforts. Of course, this depends on "appropriate". Do you design all your own memory blocks these days? It sounds as though you do not (because if you did, then you might realise that size does matter in memory design, and a 1Gb array is not just a scaled up 1Mb array, given that the internal controls on memory blocks require mixed-signal design). And of course, if you don't find an IP block that is configurable (as many of them are) to match your functional needs, then you may well find that you are just as well-off designing a new block from scratch as trying to warp an existing one to meet your new purpose and thus have to redo all kinds of block design steps. But I would not discount the real experiences that Ron Collett is basing his statistics on. There are now many examples of companies who chose the right IP, mixed it with a suitable blend of new design blocks where necessary, and achieved very reasonable increases in productivity, reduction in design risk and reduced elapsed design cycle. Making the right choice of IP vendor(s) with the right quality is of course also important (and I will say that I also work at Tensilica, as Steve Leibson does).

at 12/21/2007 9:15:18 AM, Mordon Goore said:
Actually, assuming that you are already re-using some IP blocks, then it is more than reasonable that 75% of your time would be in high-level integration and verification. This is Amdahl's law in action. The claim was that IP Reuse has "linear" scaling in productivity. (although now I hear "reasonable" increase) I disputed that, and still do. I'm not against IP re-use. That's absurd. I'm against claims that huge gains are to be had over what is already standard practice. I also doubt that an external consultant could provide more insight on this issue than could an experienced designer who knows his/her own project and the ones that preceded it. The reality is that easy-to-reuse IP like memories and uP cores are already widely re-used. By the way, I've worked as a memory designer. (in ancient times) Yes, a 1Gb array is more complex than a 1Mb array. But it is not 1000x more complex and it is certainly not e^1000x complex as was asserted. I think people just like to throw around the word "exponential" because it sounds cool. But we're engineers here, and it's totally imprecise in this case. Large memory arrays need word lines to be staged in order to drive all the way across, and columns need to be broken up, requiring more prechargers, sense-amps and muxes. But this is almost by definition a log(n) increase in complexity. Finally, I can't comment on Ron Collett's statistical analysis, because it was not presented; only his credentials.

at 12/21/2007 9:34:43 AM, Grant Martin said:
Mordon: Thanks for the clarification, and I am glad that you are a fan of IP reuse and that your issue revolves around the nature of the productivity gain function. Certainly, more from Ron Collett would be of interest here (I was not at the IP 07 conference but am watching the presentation as I type this....see Philippe's note above). But I can also say (as a past contributor, when I worked for Nortel, to Ron's statistics) that I think he does a good job of reporting the data he gets, from real design teams.

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