Leibson's Law

I’ve just returned from Maastricht, Netherlands where I attended the 2008 edition of the MPSOC (Multi or Many Processor SOC) conference held at the unbelievably beautiful 18^th-century Château St. Gerlach Hotel. For me it was four days of info-packed presentations that serve as a pretty reliable guidepost for where we are in the MP-specific evolution of system design...and where we’re going. My next few blog entries will summarize some of the most relevant MPSOC presentations.

The first MPSOC presenter was Liang-Gee Chen, a Distinguished Professor from National Taiwan University, who spoke about scalable and reconfigurable stream processing for mobile multimedia systems. Although the meat of this presentation is about multimedia processing, I think the introductory material was at least as important. Professor Chen’s premise is that there are two main forces driving MPSOC development. The first major force is simple technology push. Moore’s Law continues unabated and we continue to be able to pack more transistors, hence more functions, into each mm² of silicon. That means either building equivalent functions in less silicon—for reduced cost—or (more likely) adding functions while keeping the size of a silicon die constant.

The second major force driving MPSOC development differs depending on whether we’re discussing server-type equipment or end-product applications. Servers need improved performance for so-called RMS (recognition, mining, and synthesis) applications. End products need improved performance for so-called MMM (mobile multimedia) functions. Most important in the MMM category, according to Professor Chen, was the ability to adapt coded content to a variety of different devices. Video coding and graphics are key to this category because they involve the most computation. (That may be true currently, but there are many pattern-matching applications I can think of such as continuous-speech, face, and gesture recognition that will surely need even more computational ability looming in the future.)

However, video and graphics certainly hold our attention at the moment. The industry is rapidly evolving into the H.264 era where one video-coding system encompasses a multitude of devices running various video resolutions. H.264 SVC (Scalable Video Coding), the topic for the rest of this talk, is designed to be decodable by many different devices. “Video-coding standards such as H.264 SVC generate a bit stream that contains multiple resolutions” said Chen. Consequently, the decoding process requires more computation. This is merely the latest example of a long-term trend towards increased coding efficiency that happens to also boost the computational requirements for a video decoder.

According to Chen, there are two approaches to achieving the increased computational abilities needed by advanced video-coding techniques. The first is parallel processing using pipelining, systolic processing, task-level parallelism, instruction-level parallelism, and data-level parallelism. The second approach, which appeared about two years ago at ISSCC according to Chen, is stream processing (formerly known as data-flow computing).

Professor Chen then launched into a more detailed description of the stream processor his team is developing in Taiwan for video applications. I won’t even try to describe it to you in this blog. If you’re interested, check out the notes on his lab’s Web page.

One key point for me came at the very end of Professor Chen’s talk. His detailed presentation discussed a stream processor with a limited form of reconfigurability. The individual processing elements within his stream-processing design have multithreaded engines that can be shared between two processing elements. When a processing element is handling a task with many threads, it can be configured to use its neighbor’s thread engines to speed processing. It’s an interesting experiment. However, said Professor Chen, when the application is well-defined beforehand, his research indicates that you do not need reconfigurability.