Leibson's Law

I’m at DAC in Anaheim this week and one of my jobs is to honcho a couple of Pavilion Panels on the exhibit floor. Today’s panel was called “Will 22nm be our Catch 22?” and I thought it was a pretty interesting event. So did the 100 or so people who stayed for the entire hour listening to panel chair Joe Sawicki (Mentor Graphics) and participants ST Juang (TSMC), John Kibarian (PDF Solutions), and Lars Liebmann (IBM). Just before we started, EDA commentator and ex-EDN editor Gabe Moretti (who now runs a site called Gabe on EDA) said “I’m here because I like science fiction.” Well, I didn’t hear much science fiction from today’s panel. As Walter Brennan often said in the TV series The Guns of Will Sonnet— “ No brag, just fact.”

Sawicki set the tone for the overall panel by saying that EDA [in general] sits at the confluence of the changing nature of design. Then he asked the panel to comment on what changes would occur at the 22nm node. Finally, he said we can talk about these upcoming changes now, knowing that we will need them soon.

Soon?

Yes. Sawicki said “soon.” Because whatever it is, the 22nm node will be the one that follows the 32nm node and it will be here—according to Moore’s Law—in the year 2011. That’s three short years from now.

What challenges will we face? What lithography will triumph at 22nm? What design rules will we use? And how will this all come together?

Kibarian started the chorus of responses to Sawicki’s questions. He said that he believed that the same litho system used for the 32nm node would be used for the 22nm node. However, he said, there is not enough test silicon in the world to test all the manufacturing process interactions at the 22nm node. As a result, Kibarian believes that we will need to reduce manufacturing variability by using qualified patterns where the pattern he’s referring to is “something bigger than a transistor.” Later, during the Q&A session, Kibarian would elaborate by saying that he meant qualified patterns representing “several transistors.” He further refined that idea by pointing out that “qualified patterns” should represent a fixed amount of silicon real estate at lithographic dimensions shrink. That made a lot of sense to me.

TSMC’s Juang jumped in with a quip: “I’m going to retire by then [the 22nm node], I thought. But it’s coming too fast.” “How do we prepare for the 22nm node?” he asked. Through more accurate modeling and simulation and better modeling throughput, he answered. We will need new design methodologies using a more constrained design approach that co-optimizes design and manufacturability but this is very tough in the very dis-integrated (de-verticalized) IC design and manufacturing world of the 21^st century. (Kibarian later disagreed with the term “constrained,” which means “things you can’t do.” He much prefers the concept of “qualified patterns,” which describes “things that are known to work in a wide variety of situations.”)

Juang continued by saying that we need a business model that will allow these technology advances to happen with the existing IC ecosystem players who must help each other to develop the increasingly costly methodologies and processes given the low and falling profit margins of modern IC manufacturing. That’s a pretty darn dismal view of the state of our high-tech industry, in my opinion, but it’s probably accurate when it comes to nanometer lithography. Considering that I just paid $45 for a replacement dryer knob, perhaps the advice given to Dustin Hoffman in The Graduate was right after all. “Plastics, my boy. Plastics.” That’s the future?

Liebmann then chimed in. Although Juang had suggested that EUV (extreme UV) was a litho process possibility at the 22nm node, Liebmann said that it was clear to him that the optical process of choice would be 193nm light sources and water-immersion lithography. The lithography will be very challenging he said, but there will be no magic tool falling from the heavens.

Then Liebmann held up a Snellen chart, used by optometrists for decades to measure visual acuity. The chart has progressively smaller test on eleven lines of text. The text on line 8 can be read at 20 feet by people who have normal, average vision. By analogy we will need to extend this chart to line 17 and 22nm litho systems will need to be able to resolve such tiny text to create working chips at that node.

[Note: One of the rules for these DAC Pavilion Panels was no use of PowerPoint slides. Liebmann’s use of a real, physical exhibit was a brilliant response to this rule and he made his point memorably. Overall, I believe that the panel’s effectiveness was greatly improved by the omission of PowerPoint slides and the panel’s organizer, Mentor’s Gene Forte, agreed wholeheartedly.]