Leibson's Law

Jun 17 2008 9:35AM | Permalink | Email this | Comments (5) |
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Last week while at DAC in Anaheim I went to breakfast at Tiffy’s with Chris Jones, Tensilica’s Director of Strategic Alliances. Tiffy’s occupies the same spot it has for several decades, at the corner of Katella and South Disneyland Drive. It is the un-Disney place to eat when you don’t want to pay the official DAC Hilton breakfast buffet toll of $25. There are serial photos on the wall showing Tiffy’s when it was still surrounded by orchards. So there we are, two southern gentlemen (I’m from Kentucky, Chris is from...south of Kentucky) having our breakfast and talking when two gentlemen in the next booth stop at our table on the way out. “Attending DAC?” they ask. Possibly they could tell from our badges, our garish neon-green/black DAC tote bags, and our shirts with Tensilica’s logo unsubtly but tastefully embroidered on the breast? Yes, we are.

“So are we,” they say and hand us their cards: Dave Simmons and Steve Cowie, VP of Marketing and VP of Sales and Business Develepment at CertiChip, a Canadian company specializing in “robust circuits for nano-metric CMOS SOCs.” In short, CertiChip develops and patents logic and memory IP that is either resistant to or immune from single-event upsets (SEUs). What’s an SEU? It’s a logic error caused by high-energy particles. SEUs can flip bits in SRAM and latch cells, producing random logic errors not caused by design or manufacturing problems.

The first designers forced to deal with SEUs worked in aerospace. Hardware that flies beyond the atmosphere’s protection endures a lot of exposure to high-energy particles. Military hardware designers have long been concerned with SEUs. I wrote about such designs back when I was a regional editor for EDN in the 1980s in Colorado. UTMC down in Colorado Springs (now Aeroflex Colorado Springs) specialized in developing rad-hard ICs and I attended at least a couple of rad-hard design conferences. There are now three rad-hard RAD6000 microprocessors built by BAE Systems conducting science on Mars and about another 100 riding on various satellites in space.

But SEUs are becoming important here on earth for all digital-IC designers because shrinking device geometries make even earthbound nanometer ICs increasingly susceptible to SEU-induced errors. Intel’s processor designers acknowledged the problem when they designed DICE (dual-interlocked storage cell) pulsed latches into the Itanium processor for single-error resiliency (SER). The Itanium processor chip contains two billion transistors. They’re really small. They’re susceptible to SEUs.

Designers in the storage industry are also concerned about SEUs and SER. They tend to be very interested in ECC memory to help fight SEU-induced errors. However, you rarely get something for nothing in design engineering, which is nothing if not the art of compromise. Pulse latches and ECC memories are larger than their counterparts that lack SER. That’s the nature of the game. Most benefits have costs. The art of design is delivering more benefits and balancing those costs better than the “other” guys.

Which brings us back to CertiChip and the chance meeting at Tiffy’s. Dave Simmons sent a presentation about his company’s SER IP cells. Like prior SEU solutions, CertiChip’s IP trades off area for SER. However, the tradeoffs are perhaps not so large as other SER approaches. A normal 6-transistor SRAM or latch cell grows to 8 transistors for a memory cell that’s resistant to SEUs. Ten transistors buy you a latch cell with SEU immunity. If you go to CertiChip’s Web site, you’ll find that the company appears to be in near-stealth mode. Knock on the door and see if they’ll let you in.