Leibson's Law

I’ve written about graphene as a possible successor to silicon in electronics applications (see Diamonds on the Tops of our Chips: Is Carbon the Next Silicon?, What Makes Graphene Tick (or Conduct)?, and The Name’s Bond, Carbon Bond: Graphene FETs and Moore’s Law Scaling). Now comes word from Professor James Tour’s lab at Rice University of a non-volatile, 2-terminal graphene memory device that can store a bit. The device size is on the order of 10nm, which is much smaller that today’s smallest commercial FETs (about 45 nm). You can get a little more info on the memory’s operating modes here. Essentially, 4V across the device will write a bit by putting the device into a conducting state while 6V puts it in a non-conducting state. When on, the device conducts microAmps and when off, picoAmps. So the dynamic range of the graphene memory bit is a terrific million to one while Flash EEPROMs make do with 10:1. Sounds like magic.

And it is because the developers have yet to explain the underlying storage mechanism for the memory effect. They believe that the mechanism is a mechanical displacement in the lattice. The researchers do know that the graphene lattice needs to be imperfect for the effect to work. So far, the research has been done on hand-selected devices, needed to find the imperfect ones. The path to manufacturability is not yet charted and the interface circuits have yet to be developed. Nevertheless, a fascinating development for graphene and for “semiconductor” memory.