Leibson's Law

I’m attending International Symposium on System-on-Chip in Tampere, Finland. This is the ninth year for this chip-design symposium, and my fifth year to attend. This year, Professor Jan Rabaey of UC Berkeley gave the keynote address, on “Scaling the Power Wall, Revisiting Low-Power Design Rules.” Rabaey’s speech covered a vast amount of ground in 45 minutes and I captured as much as I could before my hand cramped up.

Rabaey started his speech by noting that chip power consumption was an issue once before, in the early 1990s. Then, there were two proposed solutions to the problem. The first was to allow power-supply voltage to become a design variable. The industry had standardized on 5V digital power suppliessince the TTL days of the early 1970s. The early 1990s saw that practice come to an end. Supply voltages are now hovering at 1V and below.

The second proposed solution was to use new design techniques including:

• Matching computation to architecture
• Preserving data locality
• Exploiting signal statistics
• Supplying energy on demand

We’ve made spotty progress in using these new techniques. Instead of matching computation to architecture, most chip designers fit computation problems to fixed architectures. I also see the inappropriate use of global data buses to move data around a chip. If there's been exploitation of signal statistics, I’ve not seen it. The most used technique has been supplying energy to circuits on demand, mostly through clock gating. I think this technique has succeeded because of the availability of automated EDA tools that can do this job. The rest of the new design techniques require mental intervention and are not automated, hence their lack of adoption.

Design fixes proposed in the early 1990s missed the importance of standby power. As Rabaey says, “Things have gotten a lot worse since then.” Design complexity has risen significantly. Supply voltages now approach transistor threshold voltages. As a result, large numbers of leaky transistors inhabit big nanometer chip designs.

“The good news,” said Rabaey, “is that EDA companies are at last on the road to a low-power design methodology.” “The bad news,” continued Rabaey, “is that nothing has been solved.” We still need to make major advances before we're truly on the path to low-power design. Power is now the dominant design constraint. For example, data center costs for Web-centric companies such as Google are now dominated not by equipment or by plant costs but by energy costs. Data centers must be located near bodies of water that serve as heat sinks for waste energy. At the small end of the design spectrum, mobile devices are now completely defined by their available power budgets.

Technology scaling (smaller device geometries) will no longer help, says Rabaey, because of silicon’s fundamental limits. Although active power density continues to be somewhat limiting, leakage power, which is growing at the same rate as computational power, is the killer. At the same time, technology scaling is actually causing more design pain—in the form of process variability, which drives chip designers to adopt wider design margins or face lower manufacturing yields. Smaller circuits are also subject to more soft errors from many causes.

Rabaey’s latest road map for low-power design now includes the following techniques:

• Concurrency galore
• Always-optimal design (no energy waste, ever)
• Better-than-worst-case design (accommodate computational and memory failures)
• Ultra-low supply voltages
• “Exploration of the unknown”

Concurrency is a good idea because it drives clock rates down, which can help save energy by allowing a further reduction of supply voltage. Always-optimal design attempts to optimize at design time, during run time, and during sleep modes. This approach requires additional circuitry. Rabaey extrapolates that today’s power-management supervisory circuits will evolve into tomorrow’s adaptive system-control circuits and will manage supply and threshold voltages for several on-chip voltage islands to deal with variability.

Better-than-worst-case design (also called aggressive deployment) moves design from the use of “design corners,” essentially worst-case design, to one where circuits operate in statistical operating regions where some errors are tolerated. This design approach requires the use of error-detection and –correction circuits. Such circuits are already well known for memory (ECC) using Hamming or Reed-Muller codes. Error-correcting logic called “Razor” has been proposed for logic as well.

Ultra-low-voltage design recognizes that the true operating limit for a MOSFET is actually about 35 mV. Rabaey suggests that we can more closely approach this limit by rethinking all of digital logic. He suggested stacked transistors and logic design based on transmission gates as likely areas for productive research.

Finally, Rabaey called the idea of exploring the unknown the “Yellow Brick Road” of ultra-low-power design. This sort of design employs radically new architectures that might employ millions of small processors on a chip, arrayed in collaborative networks. Experiments with search and recognition algorithms suggest that such imprecise networks of estimating processors might produce excellent results with very low energy consumption.