Leibson's Law

Monday was the day of the multicores at two Bay-area conferences. Early in the morning, I drove to Stanford University’s Memorial Hall to attend Hot Chips 2008, the 20^th annual conference for leading-edge silicon. I’ll be reviewing some of the presentations in future blog entries, but for now the opening remarks of conference chair Don Draper are top-of-mind for me. Draper, whose day job is engineering manager at Rambus, opened the conference by noting that fully three-quarters of the chips to be discussed at Hot Chips 2008 are multicore designs. Further, said Draper, the largest chip to be discussed had 244 processor cores and the runner up had 167 processor cores. He then invited attendees to start planning on topping that record next year. It was a thrill to attend a Hot Chips conference where the focus was no longer “¿Quien tienes mas GHz?”

Later the same day and about 20 miles south in downtown San Jose (the heart of Silicon Valley according to San Jose Mayor Chuck Reed, who opened the festivities), co-founder, president, CEO, and stand-up funnyman Jen-Hsun Huang keynoted NVISION 08, NVIDIA’s first annual love fest and conference on visual computing. It took almost no time for Huang—a fire-breathing, technophilic engineering geek if ever there was one—to put chip and die photos up on the giant auditorium screen.

“When we first started NVIDIA,” said Huang, “graphics chips were nothing more than accelerators for DirectX and OpenGL.” Now, said Huang, NVIDIA’s general-purpose graphics processing units (GPGPU) contain hundreds of programmable cores and NVIDIA has started to encourage their use as parallel programming engines by offering tools like a parallel C compiler. NVIDIA is now fully in the programmable multicore camp. NVIDIA’s current GPGPU cranks at a teraflop, which is the processing equivalent of 1000 Cray X-MP supercomputers. When new, the Cray cost more than a million dollars. Now you buy the equivalent of 1000 Crays for a few hundred dollars in the form of one of NVIDIA’s chips.

A video montage had opened NVISION 08 (“This is our language” proclaimed the concluding image in the video) and throughout the afternoon, visual demonstrations showed that we do indeed know how to use massive computing power to speak the visual languages. For example, Hayden Planetarium’s Carter Emmart smoothly drove his audience through the universe using SCISS AB’s Uniview and a variety of astronomical data sets derived from government and university research programs. It was incredibly beautiful and jaw-dropping as we sped away from the Earth and Solar System at massively superluminal speeds. Stars became clusters, which became points of light in galaxies, which then became mere points of light themselves until we stood overlooking a rotating sphere that was texture mapped with the image of cosmic microwave background radiation—the last remnants of the big bang.

Then visual-effects consultant Kelly Meyers drove NewTek’s LightWave 3D and showed us how he rendered spaceship scenes for the recently concluded dystopian television series Battlestar Galactica. Massive amounts of rendering occurred in near real time. An obvious productivity boost in an industry that lives and dies on thrift at the craft level so it can spend profusely on the marketing and partying levels.

In the evening, I read EDN executive editor Ron Wilson’s blog entry on a conversation he overheard earlier that day at Hot Chips 2008 (see Heard at Hot Chips: As design outsourcing matures, a potential problem is emerging). Wilson points out an emerging problem with outsourcing chip-level design tasks. Chip and system architects here in the US are developing system designs that implementation engineers (located anywhere in the world, not just in India and China) cannot build. “Why?” I wondered, “Are they designing chips with unobtanium?”

Not so, wrote Wilson, “Architects divorced from actual implementation tend to drift into Never-Never Land.”

Aha! My take on this problem: way, way too much system design without the rigor of system simulation to prove the ideas. And why is that? Because conventional design still uses big blocks of hand-created RTL that requires gate-level simulation for even functional verification... and gate-level simulation is way too slow when you’re designing at the architectural level. Way too slow = does not get used.

One piece of the solution, in my opinion, is the rapid adoption of multicore system design. Simulation of a system largely based on multiple processor cores can use instruction-set simulators instead of gate-level simulation, which speeds system-simulation speeds by orders of magnitude. That sort of acceleration makes system simulation practical, which means that architects will actually start simulating their system designs to prove their ideas instead of using Kentucky windage to gauge the merit of their work.

So it was truly a day of multicores. Yet another indicator of the way electronic systems design is developing.

Got multicore?