Leibson's Law

Steve Leibson Leibson's Law: It takes 10 years for any disruptive technology to become pervasive in the design community. This blog is about the disruptive technologies that either have or will win over electronic engineers, some that won't, and why. Please feel free to link to these blog entries! Written by Steve Leibson, a freelance content creator and marketing/lead-generation consultant specializing in high-tech companies, former VP of Content for Reed Business, and former Editor in Chief of three publications including EDN. See my consulting Web site at www.sleibson.com and my history site at www.hp9825.com. You can email me at steven.leibson followed by the magic email symbol @ followed by att.net.

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Sunday, November 1, 2009

Another Incremental Step Toward a Viable Phase Change Memory

Nov 1 2009 8:51AM | Permalink |Comments (8) |

After 40 years of working on phase-change memory (PCM), researchers announced...another incremental step towards creating devices that can compete with the current king of the non-volatile memory hill: Flash EEPROM. Certainly, there are PCM devices on the market now (see this blog and this one). However Flash memory, already the cost/bit memory leader by far, has threatened to leave all other memory technologies far, far in the dust as it evolves from single-layer cells (SLC) to multi-layer cells (MLC). But there’s trouble visible on the far horizon for Flash memory. The number of electrons stored in a Flash cell drops with each new lithography node and we will soon be using the charge difference between the presence and absence of a few dozen electrons to distinguish a bit. Scary.

PCM can’t perform the same trick of packing multiple bits per cell that Flash does by using variable amounts of charge to represent two, three, or four bits on one cell. One of the known and required enabling technologies for PCM to become cost-competitive with Flash memory is the ability to physically stack multiple bit cells to create 3D PCM devices. That’s precisely what researchers from Intel and Numonyx announced last week. Researchers from the two companies—who have been working on PCM together long before Numonyx spun out as a in independent company in 2008 after starting as a joint partnership between Intel and STMicrolectronics—said they will be presenting a paper at next month’s IEDM conference on a test chip that implements stackable (but not yet stacked) PCM cells.

I have written a more detailed analysis of this announcement here.

Related entries in: Flash Memory | Memory | Nonvolatile Memory |

Reader Comments

at 11/1/2009 7:02:06 PM, How about DRAM said:
Shouldnt the same limitations of flash be applied to DRAM? Both are based on charge storage. What are PCM's prospects as DRAM replacement?

at 11/1/2009 7:48:25 PM, Steve Leibson said:
PCM stores bits by heating the glass cell and switching it between its crystalline and amorphous phases. Since we're dealing with phonons for the physical heating here, I don't see PCM every getting as fast as DRAM. PCM also needs different amounts of time to write a 0 or a 1, depending on the direction of the phase change. According to a recent report on PCM by Jim Handy of Objective Analysis, PCM write speeds are comparable to NAND Flash write speeds today, with the big advantage that PCM doesn't need an erase cycle before a write. Handy predicts an order of magnitude improvement in PCM write times. We'll see. However all DRAM needs to effect a write is to drive some electrons into a small capacitor. That's a lot faster, and is likely to remain so.

at 11/1/2009 9:02:48 PM, How about DRAM charge storage said:
Ok, but isnt the number of electrons issue still applicable to the DRAM?

at 11/1/2009 10:38:25 PM, Steve Leibson said:
DRAMs store electrons that flow into capacitors over conductors while Flash memories store electrons that tunnel across an insulating barrier into floating gates so the storage mechanism is entirely different between the two. DRAM capacitors are much, much bigger. DRAMs are periodically refreshed long before much charge can bleed off the capacitor while NAND Flash is essentially never refreshed so when electrons wander off from the floating gate, they're just gone. DRAMs don't suffer from trapped charge, one of the NAND Flash cell's failure modes. In addition, DRAM designers have proven diabolically clever in finding ways to increase cell capacitance even with shrinking device geometries by exploiting the Z axis. This isn't possible with floating gates in NAND Flash using the existing planar process approach and making the gate thicker isn't an option. New materials might be an option, but I've not heard anything very hopeful as of yet. To first approximation, I don't see DRAMs running into the same sort of problems with electron starvation. Don't worry though, the designer's life when working with shrinking nanometer silicon is never easy, whether it's DRAMs or NAND Flash. And making these things at a profit, consistently, also seems a bit of a reach. Consequently, there are always researchers looking for other ways to build extreme-density memory at low cost. There's currently research into a dozen or more technologies. My own guess: the far future belongs to carbon nanotube memristors, but that's a pure guess because we don't have a clue as to how to manufacture such things at all, much less in volume.

at 11/2/2009 12:23:38 AM, DRAM vs Flash said:
Steve, thanks for the tutorial. I still find it odd, or maybe amusing, that people are willing to dump or replace Flash but not DRAM. Especially as DRAM consumes more power with the refresh. The other thing I would like to sanity check is, granting that the Flash requires much longer time for programming while the current is still comparable to DRAM, I think DRAM has to deal with far fewer electrons than Flash.

at 11/2/2009 8:25:04 AM, guest said:
DRAM vs flash, capacitance for DRAM they try to maintain ~ 25-30 fF and voltage doesn't scale so aggressively. That means just under 200,000 electrons, maintained from generation to generation. Flash doesn't maintain it so will shrink the electron number. Less than 1000 electrons tunnel in now. But refresh power is a bigger concern for bigger DRAM arrays. It's a threat to green and mobile applications. The original thinking was NOR to replace but now there aren't enough electrons anymore.

at 11/2/2009 8:40:10 AM, DRAM said:
Sure the full capacity is as high as 200,000 electrons, but if your transistor only outputs microamps and you want to operate as fast as nanoseconds, you are only going to get thousands of electrons at best. The high capacitance is becoming a waste.

at 11/2/2009 9:50:16 AM, Steve Leibson said:
DRAM vs Flash: Perhaps I misled you. Engineers can be a mercenary lot. It isn't that engineers don't want to replace DRAM. It has lots of undesirable qualities: its need for refresh is at the top of my list. But to paraphrase Sir Winston Churchill: DRAM is the worst memory ever developed, except for all the others that have been tried. Rest assured that even DRAM's reign is bound to end at some point.