Steve LeibsonLeibson's Law: It takes 10 years for any disruptive technology to become pervasive in the design community. This blog is about the disruptive technologies that either have or will win over electronic engineers, some that won't, and why. Written by Steve Leibson, Tensilica's Technology Evangelist. See my history site at www.hp9825.com. You can email me by taking the first letter of my first name, appending that to my last name, then the magic email symbol, followed by the name of the company I work for, and then a dot followed by com.

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Tuesday, August 26, 2008

Hot Chips 2008: Roofline Estimation of Parallel Processing Optimization—How to Know when You’re Done

Aug 26 2008 10:57AM | Permalink | Email this | Comments (2) |
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Sam Williams, a PhD student working under UC Berkeley’s Professor and Processor Guru Dave Patterson, gave a polished Hot Chips talk on a metric that allows undergrads (and, in my mind, overly busy design engineers) to determine when they’ve sufficiently optimized software to run on multicore parallel processors. Note that this model is about optimization, not writing correct parallel programs. "If you can't write a correct parallel program," said Williams, "you shouldn't be worried about optimizing it." 

William's concept is called the “Roofline Model” and I thought about summarizing it here, but I’d need a blog entry the length of the presentation to do it. So go get a copy yourself on Williams’ Web page.

Essentially, the Roofline model tries to pair information about a multicore processors maximum FLOPS performance with information about the “arithmetic intensity” of the problem at hand. The arithmetic intensity is simply the number of FLOPS needed divided by the number of bytes that must be transferred to solve the problem. It’s a measure of the problem’s balance between computation and data movement. Different problems have different algorithmic intensities.

Together, the maximum available FLOPS performance and the performance of the processor at different algorithmic intensities creates a maximum-performance curve. No amount of program optimization can exceed this curve. Once you hit this curve, there’s no point in trying to optimize further because you can’t get any more performance out of the processor. Here’s a curve for an 8-processor multicore system based on Intel’s Xeon processor.

 

 

The curve shows the maximum achievable performance in the upper curve. It also shows what’s achievable if you start to omit certain optimizations such as the use of SIMD instructions and heavy use of instruction-level parallelism. Using this model and an estimation of a program’s arithmetic intensity, you can quickly determine the expected performance from this multicore processing system, as shown below.

 

 

I recommend this paper to you.


Reader Comments


at 8/27/2008 2:09:48 PM, JamesF said:
"Thickness of the roofline is indicative of requisite compiler or SW complexity" I thought this was an interesting way to measure complexity of a chip. Never seen this insight before. Pervasive DataRush is writing a java engine that automatically scales java code to multiple cores. It would be interesting to see how it measures up in this roofline paradigm. JamesF PervasiveDataRush

at 8/27/2008 3:23:01 PM, Steve Leibson said:
One thing I noticed about the Roofline concept: processor clusters with higher max performance have thicker roofs. In other words, you can do very little optimization and get very poor performance. From the four examples shown in the slides, it seems the higher your Roofline, the further you can fall.

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