Leibson's Law

Alex Mericas’ Hot Chips presentation delivered some insights into low-power processor design that IBM has gleaned from designing it’s series of server-class microprocessors: Power4, Power5, and Power6. These insights aren’t new. People involved in processor design know these tricks. But perhaps they’re more solid with IBM’s weight behind them.

Here are the basic concepts Mericas espoused:

• Turn off the clock when not needed. This technique uses a few extra gates but has no other liabilities and many positives. The Power4 processor had almost no clock gating. The Power5 processor had clock gating. The Power6 processor has “aggressive” clock gating. Must be good stuff.
• Use predictive power gating to switch off unused circuits. Note that this technique can cause some real timing problems when trying to power up circuits that have been switched off.
• Dynamically change bandwidth to conserve power. Use adaptive fetching to minimize the waste of a RISC processor’s speculative operations. Use adaptive prefetching to minimize consumption of bus bandwidth.
• Use dynamic voltage/frequency scaling (DVFS) to further reduce power consumption when maximum performance is not needed.

IBM says so. Now do you believe it?