Leibson's Law

“The reports of my death are greatly exaggerated” – Mark Twain

This morning at the Globalpress conference in San Francisco, eASIC’s CEO Ronnie Vasishta discussed the problems associated with ASIC development and how these problems might be overcome. Make no mistake, says Vasishta, if we do not overcome these problems the trends say that only 250 new ASIC designs will tape out in the year 2030. It’s unlikely that ambitious entrepreneurs in our industry will accept such demise, so something has to give. Some change must occur so that more system designers can again avail themselves of custom silicon. Now eASIC is in the business of selling e-beam-customized structured ASICs, so you might imagine that Vasishta’s solution will look a lot like his company’s product. But that natural bias doesn’t change the quality of his data, which is the topic of this blog post.

Let’s consider the scary data first. The figure below shows the rise of “average” design costs through a progression of IC fabrication nodes. This data comes from International Business Strategies (632 Industrial Way, Los Gatos, CA 95030, Phone (408)395-9585, Fax (408)395-5389, ibs_inc@ix.netcom.com) and you can get an earlier copy of this graph in a report from EDAC here. From 350nm to 65nm, these average design costs rose from less than $1 million to more than $60 million. This figure, often cited, becomes more comprehensible with the breakdown in the slide.

The first thing I notice about this graph is that there are several components in these development costs. That big purple component on the top is software development. That cost is intimately tied to the rise of on-chip processor use and the emergence of SOCs. It’s no surprise at all that software development costs associated with ASIC design have increased. As we started to use 32-bit processors and DSPs on chips rather than 8-bit controllers and as the number of on-chip processors has increased in the multicore era, software costs have increased. In fact, this rise in software costs helps curb hardware-design risks and keeps hardware-design costs down by placing much of the chip’s functional development on a parallel development track and by postponing some development until after the chip has been fabricated. These big software-development costs are also unsurprising when you consider that some SOC development teams have as many as nine software-development engineers for every hardware designer. Software can be expensive.

The next largest cost component is functional verification. Again, this is not very surprising. The industry has been clanging the warning bell on this development cost for years. When you design systems consisting of hundreds of millions of transistors using development techniques that were developed to create chips a thousand times less complex (essentially keeping the design-abstraction level constant for the past 20 years), then your verification costs are indeed going to skyrocket because design engineers are forced to deal with too much detail. There are ways to tackle such functional verification costs, but these methods weren’t part of Vasishta’s keynote so I’ll leave them for another blog post. Suffice it to say that when you design complex systems at the wrong abstraction level, your verification costs will be big. Physical design and validation costs—the ones you hear a lot about in the press—are indeed large but not nearly as big as the other costs.

Vasishta proposes a solution to the problems associated with escalating ASIC design costs by positing a “new ASIC.” This hypothetical device costs less to develop than the familiar structured-cell ASIC that’s held sway for 20 years. It may be hard to remember, but this top-dog position was once held by gate arrays (during the 1980s) until ASIC design tools became good enough to allow nearly any design team that wanted custom silicon to use these tools. Before gate arrays, we had full-custom silicon that was available to very few system designers. Gate arrays really opened the market for wider use of application-specific ICs. Standard-cell ASICs won out over gate arrays in the 1990s because standard-cell development tools and manufacturing processes reached the point where standard-cell ASICs provided better silicon efficiency, better speed, and lower power consumption than gate arrays for only a little more development money. However, the relentless pursuit of Moore’s-Law scaling—which enabled the rapid rise in ASIC and system complexity—and the associated deep-submicron physical effects have made structured-cell ASIC design increasingly complex and costly, to the point where the number of ASIC design starts is indeed declining (but not just because of the design costs and complexity).

Vasishta’s new ASIC strategy invokes Clayton Christensen’s idea of disruptive technology (which Vasishta nicely adapted for this situation in the graphic below). Christensen’s concept of disruptive technology was developed from observations of the disk-drive market but it’s proved to have very wide applicability across many technologies. In their early incarnations, disruptive technologies offer such poor performance that users of existing technologies relegate the new, new thing to toy status. However, even with inferior performance, these disruptive technologies offer non-users a way to participate because of substantially lower costs.

One of the best examples of such a disruptive technology is the introduction of microcomputers and PCs. When they first appeared around 1975, microcomputers were used only by hobbyists, who desperately wanted computers to play with but could not afford mainframes or minicomputers. They could afford microcomputers, especially when offered as kits. These early microcomputers were toys compared to the other computers on the market and there was no rush by industry to adopt them. Businesses had very few employees volunteering to build their own computer from a kit. However, a growing number of individuals found that they could use these early machines, particularly Apple IIs, for word processing and spreadsheets (once those were invented). Early microcomputer performance was just barely adequate for the low end of the mass market in the 1970s. Then IBM introduced its PC in 1981 and microcomputer use exploded. The PC became the mass market’s mainstream machine.

Similarly, very few system-design companies used ASICs at first because the development technology was unfamiliar and the ASICs themselves didn’t replace that many standard parts. There was little economic incentive to climb the ASIC-design learning curve at first. However, when ASICs started to gobble up substantial numbers of “glue-logic” parts, their use increased and they became “mass-market” parts.

The IC vendors have done such a great job, however, that the hundreds of millions of transistors on today’s ASICs outstrip the abilities of many design teams to exploit the technology, particularly when factoring in the high costs of leading-edge ASIC development. This is the unhappy part of Christensen’s disruptive technology concept. As a disruptive technology evolves, it becomes increasing expensive because the mass market persistently clamors for new features and vendors rush to accommodate. Product complexity increases and vendors can sell these improved products for more money. Eventually, there’s room at the bottom for another disruptive technology.

That is the opening for Vasishta’s “new ASIC.” Initially, the new ASIC does not offer all of the capabilities of the existing standard-cell ASIC. It’s not as fast and part costs are not as low because silicon utilization isn’t as high. However, in exchange for these less desirable traits, the design of the new ASIC is easier, design costs are lower, and NRE costs are lower too.

Vasishta’s “new ASIC” is really another incarnation of the “structured ASIC,” which is an ASIC were some or all of the masks are standardized. Such standardization reduces the amount of design needed (including essentially all of the physical design) and therefore reduces design costs. I wrote a 2-part article last year for EDN’s sister publication Microprocessor Report titled Structured ASICs: Dead or Alive? I conducted several interviews with seasoned structured-ASIC veterans for that article. Based on those interviews, I concluded that structured ASICs offered a middle ground between FPGAs and standard-cell ASICs, but the existing product offerings had not managed to displace those other two competing technologies for a variety of technical and business reasons.

It may well be that prior structured-ASIC technology may have been too immature to displace the other “mass-market” alternatives. However, that doesn’t mean that structured ASICs will remain uncompetitive. Companies like Vasishta’s eASIC continue to bring new ideas to bear on the technology, which improves the product offerings. According to Christensen’s ideas these improved products may eventually become “good enough” (Christensen’s term) to appeal to non-users.

That takes us back to the issue I originally discussed in the first paragraph of this long blog entry. System designers are increasingly becoming non-users of standard-cell ASICs because of cost and complexity issues. These people would like to use something that offers better speed and silicon utilization than FPGAs with development costs substantially below that of today’s leading-edge, standard-cell ASICs.

If eASIC succeeds in developing such a product, says Vasishta, then non-users will become users and the number of ASIC designs will increase, as shown in the following graph. The motivation to use such a product is certainly there. The challenge is to bring such a product to market successfully. If eASIC (or another vendor) succeeds, then we my indeed see the return of the ASIC, as Vasishta conjectures in this final graphic.

 (Full disclosure: My employer, Tensilica, partners with eASIC. That doesn't change Ronnie Vasishta's presentation or my discussion of it one bit.)