Leibson's Law

The last presentation I listened to at the Electronic Design Processes Workshop last week was from Atrenta’s CTO Bernard Murphy. His was a very practical presentation in my opinion and he effectively asked the question: “How much theoretical performance are you willing to give up to tape out your design and get it into silicon?” It’s truly a practical question. Engineers intuitively know that the closer they try to get to perfection, the longer it takes. Push silicon technology hard to get clock speed or low power and you’ll spend a lot of time chasing the problems that crop up.

Are you willing to settle for good enough and not perfect? Are your competitors? If so, then who wins the market? The perfect chip that’s not yet available or the imperfect chip that’s in stock and gets the job done? Intuitively, I think you already know.

So if you’re not competing at the silicon level, where can you compete and win. Murphy’s answer, one I strongly agree with, is that you need to compete at the architectural level. Architectural-level design and analysis tools, automated assembly tools, and platform architectures are the future from Murphy’s perspective. As a system designer myself, I can only agree with him. Strongly.

Silicon tricks have run out. Study what it takes to get extreme ultraviolet fab equipment running like I have and you’ll be amazed if the technology ever becomes practical. We’ll be building graphene nanochips first, I think. So consider this. As Murphy said, you’ll be much better off if you can develop a system architecture that doesn’t require every drop of performance you can get from the underlying silicon. Better time to market. Lower power. More reliability. Better immunity to on-chip variability and process variation. All very attractive. No?