Analog IC design on the cheap

One of the greatest things about National Semiconductor’s analog design flow was what they called planet runs. A planet run is single wafer that has maybe 10 or even 100 different IC designs on it. So rather then cost fifty to a couple hundred grand for a mask set (analog mask sets being cheaper than fine-line digital by a wide margin), the cost of the prototype was one-tenth to one-hundredth for the department. Each process was given a different planet name— Venus was CMOS-7, I think. So every 6 weeks or so all the IC designers have a free wafer they could prototype their designs on. Since I was in the amplifier group even a single wafer shared with all the other groups would still yield a thousand amplifiers, since they were so small. This is just great if you work at National, but what about the rest of us? Where is our low-cost planet run? Well it turns out that since 1981 there has been a company called MOSIS. They do the exact some thing, put your IC onto a shared mask so you only pay a small fraction of the mask cost.

They have processes (including analog) and they source wafers from:

• AMIS Fabrication Processes. The AMIS processes available through MOSIS include 1.5 µm CMOS, 0.7 µm high voltage CMOS, 0.5 µm CMOS, and 0.35 µm high voltage CMOS.
• austriamicrosystems Fabrication Processes. Processes offered by MOSIS through austriamicrosystems include 0.35 µm CMOS, high voltage CMOS, and SiGe BiCMOS.
• IBM Fabrication Processes. The IBM fabrication processes available through MOSIS range from 65 nanometer to 0.25 µm in CMOS, and from 0.13 µm to 0.50 µm in SiGe BiCMOS.
• TSMC Fabrication Processes. The TSMC logic and mixed-mode fabrication processes available through MOSIS include 0.35 µm CMOS, 0.25 µm CMOS, 0.18 µm CMOS, and 0.13 µm CMOS.

Wow, you can even do silicon germanium.

Now National Semiconductor used Cadence, pretty much the monopoly powerhouse in analog IC design. I asked Dave Tamura, a CAD tool manager what National pays for a seat of Cadence and he said, “We don’t know, and Cadence likes it that way.” He was being a bit facetious but explained that there was no standard seat, it depended on how many unique little features and tool flow options and other stuff were needed by a particular designer. In any event I can pretty much guarantee that the Linux workstations and Cadence tools must cost from 50 grand to 150 grand for each and every IC designer. That would seem to make the cheap prototype service MOSIS offers a moot point— why look forward to spending only 10 or 20 grand on your prototypes if it costs 50 grand for the software? The thing is that you don’t need Cadence to design analog ICs. Linear Technology uses a highly optimized form of P-Spice, and that is only to match the particular process they use to the results the Spice runs give. If you are Bob Pease you can design ICs without Spice. For that there are some cheap layout tools (free to $1500) that will generate the tape-out files that you can send to MOSIS. If there is any interest I will lasso up a bunch of IC designer pals that have designed on the cheap or free tools and let you know how they did it. Now that I have found a way to get a planet run even though I don’t work at National Semiconductor, the desire to design and build a custom IC for under 10 grand seems within reach.