International Test Conference in Silicon Valley, this week Oct 23-25, 2007

I just registered at the International Test Conference here in Santa Clara Convention center. This is more testing for design then instrument test. Agilent, Tek, none of the bench-top folks are here. The exhibits are free but the sessions cost money. After spending ten minutes searching the website and my program that I got when I registered, I have to assume the prices are a secret since they are nowhere to be found. Oh well, bring a few Jacksons, that should cover it. It runs from Oct 23 2007 to Oct 25. Some things that caught my eye:

SESSION 16 Wednesday, 10:30 to 11:00, Room 203/204

New Tests for PLLs D. Appello, STMicroelectronics (Chair) S. Sunter, LogicVision (Coordinator)

16.1    Real-Time Signal Processing—A New PLL Test Approach H. Okawara, Verigy

16.2   A Methodology for Systematic Built-in Self-Test of Phase-locked Loops Targeting at Parametric Failures G. Yu, P. Li, Texas A&M University 

16.3   A Low-Cost FFT-based Jitter Separation Method for High-Frequency Clock Testing T. Yamaguchi, M. Ishida, Advantest Laboratories; H. Hou, D. Armstrong, Advantest America; K. Takayama, Sony; M. Soma, University of Washington

PLL testing is cool since they have a time domain problem and high frequencies. Tey need to watch their PLL start up and then lock in. This can take billions of cycles. A real time domain anaysis can take a week to run. So antying that crosses over the time and frequency domain to make this job easier is pretty neat.

Ballroom C, Corporate presentation, 2:30 to 3:00: C5.2    GuideTech –S. Tabatabaei  Sub-Picosecond Jitter and Phase Noise Measurement

Measuring anything less than a picosecond is cool, I don’t care who you are. And this segues trith into

20.3 Wednesday 3:00 to 3:30, Room 203/204

20.3   Common-Mode Currents in Semiconductor ATE Instrumentation W. Bowhers, Merrimack College

This is cool too—if you have every tried to measure something while common mode currents screwed up the measurement this might be a good presentation. And is has the college panache to it as well.

 Wednesday 4:00 to 5:30 Ballroom D; Panel 6 Where is Car IC Testing Going?  (Moderator)   Y. Okuda, Sony (Organizer) P. Nigh, IBM

To boost car safety and comfort, car ICs are going to highly integrated systems, which will shift the car IC business model to models similar SOC, chipset and fabless. The panel will debate what is changing for car IC testing and explore the solutions. Panelists are from US, European and Japanese companies that supply car ICs. 

As a former auto engineer I am fascinated by what it takes to make silicon live in an automotive environment. After all, back in 1970s I was given responsibility for the most unreliable part in a Ford car—the ignition module. I said to make the board out of FR4 instead of paper-phenolic. They decided to add a pound of sand under the board before it was potted in. I left to work in Silicon Valley. Quality is Job 1? Yeah, right.

OK, on Thursday we also have some cool stuff going on.

Thursday 8:30 to 10:00, oom 203/204 SESSION 24 DFT and Analog Testing; P. Cauvet, NXP Semiconductors (Chair) S. Mir, TIMA Laboratory (Coordinator)

24.1 Low-Cost Automatic Mixed-Signal Board Test Using IEEE 1149.4; S. Sundar, B. Kim, University of Alabama; T. Byrd, F. Toledo, Automated Circuit Design; E. Beskar, S. Wokhlu, R. Rousselin, G. Kendall, D. Cotton, Texas Instruments  

24.2   Efficient Simulation of Parametric Faults for Multistage Analog Circuits F. Liu, S. Ozev, Duke University 

 24.3   Using Built-in Sensors to Cope with Long-Duration Transient Faults in Future Technologies C. Lisboa, F. Kastensmidt, L. Carro, G. Wirth, Universidade Federal do Rio Grande do Sul; E. Henes Neto, Universidade Estadual do Rio Grande do Sul

Hey, I am the analog editor so analog is what I pick. There are dozens of other sessions but I am sticking to the analog ones. After that early morning analog experience how about a nice invited address by another cool college professor:

1:15 to 1:45, Exhibit hall D

What’s The Trouble with Analog/Mixed-Signal Test—Not Enough Feedback; Gordon W. Roberts, James McGill Professor of Electrical and Computer Engineering, McGill University  

The engineering issues that an analog and mixed-signal IC test engineer face are identical to those encountered by a system’s design engineer. Moreover, the test engineer often does not see his or her job activity as one that involves design, as they work without structured design flows or test-specific CAD tools. As a result, they often lack insight into what successful design engineers all know, that is, a circuit or system must implement some form of negative feedback to be robust, time-invariant and accurate. This talk will look at the shortcomings of some of the most popular techniques used by the analog test engineer to enhance their test such as load board circuits, loop-back and the golden-device approach, and other DFT techniques such as BIST, and use the negative feedback principle to highlight the path forward.

And after that lofty presentation lets get back down to earth with this:

Thursday 2:00 to 3:00 SESSION 32 ADC Test; N. Khouzam, National Semiconductor (Chair) G. Roberts, McGill University (Coordinator)

 32.1   A Stereo Audio S? ADC Architecture with Embedded SNDR Self-Test L. Rolindez, J-L. Carbonéro, D. Goguet, N. Chouba, STMicroelectronics; S. Mir, TIMA Laboratory

 32.2   Sigma-Delta ADC Characterization Using Noise Transfer Function Pole-Zero Tracking H. Kim, K-S. Lee, Texas Instruments  

32.3   A Fully Digital-compatible BIST Strategy for ADC Linearity Testing H. Xing, D. Chen, R. Geiger, Iowa State University; H. Jiang, Texas Instruments

There is some stuff Friday but the exhibits are closed and it is pretty specialized stuff. Check out the website and see if you want to go. Like I said, the exhibits are free but the sessions may cost you something.