Fairchild Power seminar, off-line switchers, magnetics, FETs, motor-control and more
I told you about the Fairchild Power seminar a couple months ago and it turned out to be a great event. Here in San Jose it was in the Sheraton Hotel in Milpitas, a stone’s throw from Linear Tech and Intersil. I wondered if Fairchild was going to have local people do the seminar, but no, they sent in experts in the subjects from LA and the Midwest. In addition to a continental breakfast you could have joined the experts in a great lunch, way better than the rubber chicken fare that is often seen at hotel seminars.
The first presentation was about asymmetric half-bridge converters (AHB). Carl Walding, a field applications manager from Illinois explained the detailed design techniques to make an off-line power supply that can deliver hundreds of watts at 90% and better efficiency. Carl went on to walk us through an example design for a 400-volt input, 24-volt output 200-watt switcher. The 400V dc input was predicated on the fact that you may well have a power factor correction (PFC) circuit in front of the supply that would take ac in and make a 400-volt dc bus.
Carl Walding explains the asynchronous half-bride converter.
The big thing that I learned was that one cause of power loss in FETs is because you switch it on and discharge the FETs internal drain-source capacitance (Cds) across the FET. I asked about the more traditional switching loss where the slope of the transition is not a brick wall and Carl explained that, sure, that is still a loss, but FETs switch so fast these days it is the discharge of the drain-source capacitance that often predominates. Like all analog things, it depends on your specific design. One of the cool things about the asynchronous half-bridge is that it is a zero-voltage switching (ZVS) architecture. You only turn on the FETs when there is no voltage across them so you are not wasting the charge in the drain-source capacitance. I have designed half-bridge power supplies that used two capacitors across the bus voltage to make a half-rail for the ac currents and voltages. What Carl did was hang a transformer off the rail and then use just one capacitor in series with primary. He showed how clever design with unbalanced center-tapped turns in the secondary can even eliminate any dc magnetizing current in the primary. This makes the output inductor bigger so you trade off transformer size to inductor size to get the best trade-off. Since the output inductor in an asynchronous half-bridge is already one half the size of other architectures, this is still a good trade-off. In order to get zero-voltage switching (ZVS) Carl then showed us how to engineer the transformer to have enough leakage inductance to sustain the energy transfer long enough to let the voltage across the FETs drop to zero before the controller switches the FET on. It should be noted that the control chip is not sensing the voltage across the FET, you just design the transformer with enough leakage inductance to insure that you get zero-voltage switching for all but the lightest loads. This converter also uses an inductor in the secondary to lower the peak currents in the diodes. This also helps efficiency and is a benefit over the LLC (inductor-inductor-capacitor) type of supply that has no output inductor to limit peak currents in the diodes or ripple currents in the output capacitors. This was a hard-core technical presentation, including the way to wind transformers in order to get the right leakage inductance so the circuit will work properly. This talk was based on a paper and slide presentation by Hangseok Choi, an engineer that worked in Fairchild’s Korean division. One thing I loved about the presentation was that there were absolutely no Fairchild part numbers in it. I know they make controller that would work and it is obvious they have a selection of FETs as well. The only reference to a controller part number is in the paper, where they mention the FSFA integrated FET and controller IC. My notes show you can get 200-watt supplies with the part with no heat sink and 400 watt supplies with a heat sink. Oh, and did I mention—93% efficiency. Sweet. If you go to one of the remaining seminars your book will have both the presentation and the original paper, neither of which are on-line yet.
Carl continued with the second presentation, how to design a low-power auxiliary supply like you might use to make 2 to 5 watts off the line in order to power a remote control receiver or other low-power circuit that has to be very efficient. The big constraint in this application is low-cost. What is interesting is that the huge increase in the price of copper means that it is cheaper to use a switcher than a liner supply. Carl explained that most people use flyback converters for this. The cool thing about this circuit is that it is not clocked at any particular frequency. What the system does is let the transformer ring out and when the voltage dips to a minimum then the FET closes again and this gives the same benefit as the previous design—the losses due to discharging the drain-source capacitance are minimized. This circuit cannot do zero-voltage switching, but it gets as close as possible. Now since this circuit is not clocked, there is problem when you get to light loads. As the load gets lighter the time period for the transfer to dump its energy gets shorter and shorter and the frequency climbs to speeds that are not practical. What Fairchild does is make parts that blank out the early rings in this low-load condition. Then they catch maybe the third or forth ring and turn on the FET at that minimum. This circuit uses an aux winding to deliver a replication of the secondary signal to the chip. You make a circuit to rectify and smooth this signal out a bit. What I like about this circuit is that there is a separate pin on the chip for feedback. I assume you could filter the aux winding even further and have a poorly regulated supply. In this example they used an opto on the secondary to feedback the actual secondary voltage and provide tight regulation. Another cool thing about this circuit is that the frequency will also change a little with input voltage. Since you usually use smaller input capacitors for low cost, the input voltage is a bit “lumpy”. These lumps modulate the frequency of the supply so that it spreads out the EMI signature and makes it easier to pass FCC. Carl admitted you only get a dB or two, but heck, every dB helps. The part they used in the example was a FSQ510. Just like the previous example, they showed how to design the transformer. Since leakage induce in a flyback is a pure loss component, this transformer minimized leakage inductance, unlike the earlier design where you put in leakage inductance on purpose. Carl also showed how to add a few components to put in under-voltage-lock-out (UVLO), so the power supply will not come on until the input voltage goes above a threshold. He also showed how to add a little linear regulator to the aux winding so you could power the chip or other chips, perhaps in you PFC or main regulator. Efficiencies for this circuit were about 83% over most of the load range. Carl then showed some thermal camera images that showed where the heat was. As is common with modern parts, the output diode got way hotter than the chip doing the primary switching. This presentation was based on a white paper by two engineers in Fairchild’s Korean division, Jin-Tae Kim and Gwan-Bon Koo.
Joe Roy explains power-factor-correction (PFC) at the Fairchild Seminar.
Next up was Joe Roy, a senior applications engineer out of Indiana. He walked us through how to design a boost-mode power factor correction (PFC) circuit. Joe explained that a boost-mode PFC convert could operate in continuous conduction mode (CCM), boundary conduction mode (BCM) or discontinuous conduction mode (DCM). Since you lose PFC in the discontinuous mode that is pretty easy to toss out. CCM gives the best power factor but the control is more complex. BCM has a simpler control and good PFC and total harmonic distortion (THD). Other benefits of the BCM are that the FETs are switching at zero current. In addition, the FETs are switched at zero voltage whenever the ac waveform is less than one-half the output bus voltage. Just as important, the inductor gets smaller by about 1/3 and the diodes can be cheaper as well. Like the flyback, this converter is not running at a fixed clock. The controller is trying to make the input current to the supply a sine wave that is in phase with the ac voltage. This is the definition of good power factor. Normal supplies don’t draw any current until the voltage gets almost to the maximum, then a large spike of current is pulled in to top off the big dc input capacitors. A PFC circuit takes in rectified ac, as a series of “lumps” that go to zero 120 times a second. When the voltage is low, the circuitry will keep the pulse on until the proper portion of current is drawn, then open the FET and let that current be boosted up to the output bus voltage. Joe went on to show how having two phases in the supply can also be a big benefit. It can make the output capacitor have far less ripple and hence, be smaller, as well as allowing the circuit to drop out or “shed” one phase under light load conditions to improve efficiency. One thing Joe warned about was that you have to insure the current s in each of the two phases was identical or you might loose the efficiency advantage of the two-phase design. He pointed out is was better to put a current-sense resistor in each of the two phases rather than use a single resistor, since the peak currents during the overlap period would cause you to use a higher power resistor than just a factor of two. This design uses discrete FETs and a FAN9612 chip. There are some cool features in the chip such as the way it handles sudden transient loads. This helps to minimize the size and cost of the output capacitor. The design example Joe walked us through is a 400-watt two-phase PFC circuit that takes in 85-265 volts ac and outputs 405 volts dc. It would accept line frequencies of 47 to 63 Hz and the minimum switching frequency would be 45 kHz. This is a good example of digital power. Joe didn’t go into the presentation crowing about how this was digital and somehow better than analog. He pointed out that doing some of the control was better suited to digital and that is what the chip does, whereas much of the chip is still analog. This presentation was based on a white paper by Chris Bridge and Laszlo Balogh.
Carl Walding then took over for a great presentation about selecting MOSFETs to minimize losses. This was based on work done by Jon Gladish an application engineer. He used TCAD, a Synopsis simulator, to help understand the losses in FETs. The cool thing about TCAD is that you model the physical FET, it is not a SPICE simulation. The presentation was interesting because it showed the methods that FET manufacturers use to minimize gate charge and bond-wire inductance. The simulations also showed that the Fairchild SyncFET, a FET that has a shottky rectifier built in, would perform better than a discrete shottky since it is “inside” the bond wire inductance of the FET. The TCAD simulations showed how source inductance, whether bond wires or external traces can cost you percentage points in efficiency in a modern switching power supply. Another new concept for me was gate bounce, where the fast turn-off of a high-side switch in a buck regulator causes the switch node to rise, and that rise is couples across the Cdg and Cgs capacitances of the low-side FET, turning it on. If the dv/dt of the voltage is fast enough, and impedance on the low-side FET gate is not low enough, the low-side FET may turn on. Carl showed that to look for in your switching waveforms to tell that this is happening. We Silicon Valley attendees got a bonus because Art Black, an applications manager here in San Jose was in the audience and he could tell us some of the details of the TCAD work as well as things he has learned doing similar simulations. These Fairchild people are hard-core, I am so glad I went to the seminar.
Just before a great lunch Sandy Chotiner, a senior field applications engineer, wanted to give a presentation about Fairchild’s products. This is the only presentation I was a bit uncomfortable with. When you ask us to pay 75 dollars to see a technical presentation we really don’t want to get a sales presentation. That is not a part of the bargain. Fortunately the tech presentations went long so Sandy’s sales presentation was only about 10 minutes and he just pointed out some new areas like point of load (POL) and other parts that Fairchild makes. They supplied a CD with the entire Fairchild selector guide on it so I could always rely on that when it is time for me to find parts. I think the presentations should be about design techniques, not parts.
Sandy Chotiner telling us about Fairchild’s product portfolio, but only briefly.
After that great lunch, we got back to hard-core technical presentations. Carl Walding took over for a paper about the thermal characteristics of the power quad flat no-lead package (PQFN). The work was done by two engineers in Fairchild’s Philippines operation, Marlon Bartolo and Erwin Almagro. Carl presented the huge amount of work these guys did to determine the effect on solder quality, copper area and vias on the ability of the package to transfer out heat. The big take-away was that doing a solder stencil over the full pad area makes for too much solder and you will get balling and bridging and other issues. By using a stencil that has a grid of patches that cover 60% of the area you do get more voids, but the great thing is that the solder voids do not appreciably reduce the heat transfer. Even 80% voids still transfer most of the heat out of the package. Another take-away was that if your pick-and-place machine puts the part down 50% off the pad, surface tension would pull the part back onto the pad. What is more serious is the Z-axis travel. If the machine smashes the part down on the board it will displace solder and cause a bad joint. The part should be dropped on the solder paste with almost no downward force. Also studied was the reflow temperature— you have to keep it under 260 degrees C but you can’t make it too cold or the solder will not bond. As to using vias in the pad, their work shows that 2 is better than 4 but there are diminishing returns after that. You can squeeze 12 vias in under the pad but the improvement over 9 vias in hardly noticeable.
After this Joe Roy gave a presentation about magnetics based on a paper by Majid Dadafshar, an FAE out of Arizona. The presentation explained the myriad trade-offs between ferrite compositions, core shape, air gaps, and winding methods. The talk covered switch ranges from 10 kHz to 3 MHz. Topping things off, Joe explained the temperature effects and contrasted how some cores like open-E types let you get the heat out of the core and winding, while a toroid lets you get the heat out of the winding but not the core, and a pot-core lets you get the heat out of the core but not the winding. This affects how you design the transformer in order to make sure that both the core and windings have adequate cooling. You would use low loss cores for a toroid and low loss windings for a pot-core. E-cores fall in between but have higher radiation and leakage. All good stuff and there was not a Fairchild part number in the whole presentation. This paper was well worth the price of admission.
Joe Roy stayed on to give the last presentation, a great one about reducing torque ripple in brushless DC motors. This was based on a white paper by Shucheng Wang, a technical and marketing engineer in China. Joe confirmed what I had heard about the difference between brushless dc (BLDC) and brushless ac (BLAC), also called ac synchronous motors. I knew that BLDC motors are fed a set of trapezoidal waves that are easy to make simply by the switching of FETs as the rotor activates hall switches. BLAC motors are fed three-phase sine waves and are much smoother and better for servo control because they do not cog. I was not sure if the motors were different or just the excitation, but Joe confirmed that if you spin a BLDC motor and look at the winding voltage it will be a trapezoid. If you spin a BLAC motor you will see three-phase sine waves. Now the cool thing about this presentation is that Joe pointed out that if your control system could make those exact same trapezoids that the BLDC motor puts out, then there would be no ripple torque and no cogging and no noise. Since you are switching the output transistors much faster, it makes sense to have FETs with this modified sine excitation, rather than using IGBTs like ac induction motor inverter uses. This design used a Fairchild three-phase driver-power stage integrated into one part, the FSB50450. Fairchild does not make microprocessors to create the control algorithm so they were agnostic on what you could use to do the math. They used a Toshiba TB6551 controller in this experiment. The results were great, with torque ripple reduced by 50% or more. Acoustic noise also dropped which was essential in this experiment since it was powering an HVAC fan that needed to run quietly. You could also expect less vibration and higher reliability. There was also a nice discussion with an audience member about hysteretic motors. Joe said that they would eventually come into wider use. Apparently there were European patents that tied up the technology so that no one in the US wanted to develop drive techniques since they would need to pay to use them with a hysteretic motor. The big drawback with hysteric motors is the acoustic noise, so maybe these drive techniques can quiet them down like BLDC motors.
All in all, this was a day very well spent. I met a lot of cool people, learned about FETs and switchers and motor control and transformers and saw what Fairchild is doing in the power space. A great day and I hope they keep giving these hard-core seminars.
