Darnell Digital Power Conference, Monday

The Darnell Digital Power Forum is running Monday through Wednesday, Sept 15-17, 2008. I just caught the Monday sessions and they were great.  The conference started out with Deepak Savadatti from Primarion in a paper titled “Digital Power From Revolution to Evolution”. He indicated that digital power has reached an inflection point now that Infineon has bought Primarion and there is a multinational semiconductor company offering a broad portfolio of parts, both conventional and digital. He indicated that digital power offers the telemetry features you would expect from a digital chip along with cost parity to analog solutions.  He pointed out applications of digital power chips in graphic cards, servers and hand-held devices.

The next presentation was Chris Young from Zilker Labs. His presentation was a digital power roadmap for 2010 and beyond. He had a great diagram showing that the silicon size of a 100 pF capacitor and an 8-bit microcontroller were about the same, with an A to D converter being about ¾ the same size and a bond pad being 1/4^th the size of the A to D.  He pointed out that while Intel might be going to 40 nm line widths soon, digital power tends to use line widths of around 250 nm due to mask costs and die production costs. He predicted that total cost would be equal to analog by 2010. He also pointed out some of the significant ease-of-use features in the development environment, the (usually) Windows application you run to develop the particular outputs and functions of your chip. This can include auto-tuning to your particular design, where you do not have to do anything, the development systems will figure out the compensations for you. Like most every digital power advocate, Chris also points out the benefit of digital power is in the diagnostics and fault response you can get from having a chip that communicate to a host and reports currents and voltages and temperatures. A crusty old analog dog like me got a chuckle from the slide that talked about how analog parts use an “analog dataflow”, when I see the two as really meaning different domains, a continuous time domain where time does exist, and a sampled data system that engineers have used since the days of Shannon and Nyquist.

Next up Monday morning was Randy Malik from IBM, a real digital power proponent. He pointed out all the products that have gone digital in our lifetimes, Computers, A/V equipment, consumer products and portable equipment, motor drives, and TVs. He noted that power seems to be the last bastion of analog and that it too is due for a change. Randy pointed out the power management features of digital power as well as the hoped-for improvements in operating cost. This combined with future EPA (environmental protection agency) regulations on efficiency and the feature-rich nature of digital power. He showed a chart that had digital power costs not rising as you add features while the analog power chips would scale cost linearly with features. Randy mentioned that one major benefit of digital power was that you could use the same module for different projects, meaning the hardware could be the same and you can just reprogram the digital chip to provide different voltages. He also pointed out application such as non-linear control of power factor correction that you can do in digital but not in analog. He also pointed out that you could modify the EMI profile of your design in a digital power system. He pointed out that minimizing input power is the key differentiator and that “plug to processor” efficiencies from ac to dc are only about 76% today. He also pointed out that digital power allows server racks to be shut down for virtualization and that the I2C or PMBus can be used to help figure out what happened when the system hangs.  The only exception I took with the speaker was that he referred to a PWM signals a digital signal when it is really analog. A PWM signal is very dependent on the amplitude, and hence is an analog signal, not a digital one.

The next morning speaker was Arthur Howard, a private contractor representing the EPA. This is the great thing about conferences like this, that you can be exposed to a very important consideration for power supply design that is not coming from your customer. Arthur detailed the Energy Star ratings in place and those that are proposed for power supplies from 1 to 200 watts. He also detailed proposed rulemaking for server farms. He also detailed rules for battery charging systems. He noted how redundant power systems can hurt efficiency since it tends to make both power systems operate at low load, where efficiency is always reduced.

The final morning session was from Michael Briere, a consultant working for International rectifier on GaN (gallium nitride) transistors. He noted that the worldwide energy consumption was projected to rise by 40% in 15 years. He said this represents a 4 trillion dollar opportunity for power vendors. Turning to GaN, Michael pointed out that key enablers are low-cost substrates, not sapphire, but silicon, as well as low cost epi (epitaxial) growth to make the GaN itself. He mentioned that IR is using 150 mm wafers but they have found no real hindrance to moving to 200 mm wafers. He noted that one thing that has held back SiC (silcon carbide) is its higher cost. He pointed out that digital power is already a reality in motor drive modules. He had an enticing slide of a Linear Tech power module and a projected equivalent module that was about half the size when using GaN power transistors.

I caught lunch with Sean Azimi from Magnetics, a private company that makes ferrite cores, powder cores and tape core magnetic devices. Sean works the west coast as an FAE for Magnetics and after stints at Intel and Quest, had nothing but good things to say about Magnetics and their products. He did verify something that my dad told me—there is nothing that can replace direct personal meetings with customers. Sean said that email can help fill in some questions, but there is no substitute for meeting the customer directly and developing relations beneficial to that customer’s goals.

The afternoon session started out with Par Ingvvarsson of Ericsson Power Modules. He showed results from calculated MTBF (mean time between failure) studies for analog and digital power modules. The digital power modules had slightly better cMTBF. As he pointed out, there has not been enough deployment of digital power modules to deduce a demonstrated MTBF. Even more important, Par showed data taken from temperature and HALT (highly accelerated life testing) where the memory system in digital power chips suffered no failure even after temperature extremes and temperature shock.

Next up was Analog Devices with a nice presentation of a real-world digital power system using an interleaved two-switch forward converter topology. Like most digital power presentations efficiency was stressed, and it was pointed out that shedding phases was possible. This is where you have a multiphase controller and when you have light-load conditions, the digital controller turns off one or more phases and disables that inductor or winding from contributing to the output capacitor. The presentation was part-specific and veered to an advertisement so, in keeping with EDN’s editorial standards, I won’t mention the part number, but it is good to know that ADI has a state-machine type of digital power chip. This one had 7 PWM outputs that could operate as fast as 700 kHz.

Next was a Fairchild presentation on the basics of microcontrollers. I think the subtle subtext to this presentation was that you could always hang a cheap 8-bit micro on your analog power system and have the telemetry and fault monitoring of a digital power chip. The presenter was very skilled but unfortunately, the material was very basic, and more suited to a high-school career fair than to working engineers. Still there was a great slide where he showed an ac-dc converter example and noted that the micro was on the primary side and that you would need isolation to send the data over to the secondary side. This got me thinking about that very issue, how all these digital power chips would handle the isolated case. Thankfully Analog Devices has a great set of digital isolation parts, several that work with bi-directional I2C bus, and TI also has isolators based on capacitive technology that should be very easy to interface to your system.

After the separate presentations was a roundtable chaired by Don Tuite. The question before the panel was “When will digital power become mainstream. Chance Dunlap from National Semiconductor said 2018, while other presenters guessed more like 2015. Of course the question begs the defining of both digital power and mainstream. One telling sign was that the one person on the panel that seemed most skeptical about digital power was Brian Zahnstecher, the fellow that worked at HP in their server division, the main customer base for digital power at this time. [Update– see the comments– I may have misinterpreted Brian’s attidude.] Whereas the representatives of TI, Zilker, and Maxim seemed more upbeat about digital power, Brian seemed much less enthused. Most every representative from the semiconductor makers had mentioned phase shedding as a power efficiency feature that can be implemented in digital power. Brian brought up a good point, saying he was not interested in phase shedding but in phase adding, since it is easy to drop out a phase under light load but it is much more critical to add that phase back in again in time to catch a load peak. Another thing that concerned Brian was a digital power chip that had all kinds of features that he didn’t need. It was amusing when a conference attendee in the question-and-answer period chided Brian, saying “Get over it!” since the features were put there for the big customer and it did not cost anything for that extra feature, indeed it would cost more to take it out. Brian replied that he was with HP and they were the big customer. In other words, it seems that the digital power people are offering features that are possible with digital power, but that these features may not address actual customer needs.

I also heard from a couple of friends that were attending he conference. Bob Thomas, an engineer with Cisco Systems pointed out that it was great to talk about disabling phases and CPUs when you are from the semiconductor company making the power chip. But when you work at a system house like Cisco and can walk down to the cubicle with the software guy and tell him you want his to power down the CPU periodically to save power, you can see from the software guy’s reaction that this is not as easy as the power chip vendors indicate. Indeed, another friend, National Semiconductor chief technologist Dave Anderson told me that one thing unstated in all these discussions about shutting down racks and virtualization is that there is one prime directive in the server farm business and that is “Uptime”. If you are going to complicate the system with power cycling that causes uptime problems there is no chance for that power savings to become adopted, since keeping the server up is far more important than saving a few dollars. People will pay for uptime, while power savings is an operating cost factor only of concern to the data center. Now, as some presenter noted, there are data centers where the power company has told they can have no more power than they are already using. This means that to increase capacity, they have to save power. It reminds me of the ACPI power standard in PCs. When Microsoft first started putting power management into the drivers, it caused no end of problems and untold crashes and blue-screen-of-death experiences. Eventually, all the bugs have been worked out and a PC can do basic power management. But the people in high-uptime data centers cannot put up with a learning curve that brings down servers. It will be a few more years, maybe a decade, before data centers are willing to risk downtime by aggressive power management.

Now it might be best to point out that digital power is suffering from what Gartner calls the hype cycle. When it first hit a few years ago, the digital power people were, well, digital, saying that everything was going digital and there was going to be no analog power left and anybody that did not see this was a dinosaur. Naturally, product adoption is analog just like every other natural process in the universe. So the adoption of digital power has been far far less than predicted by the purveyors of the chips. Chance Dunlop from National noted that companies like Potentia and others had gone out of business before digital power became mainstream.

To ask when digital power will become mainstream is a bit confusing. If digital power means having an I2C bus so the chip can talk to a host, well that has been going on for 5 or 10 years and is already mainstream. Lithium-ion battery chargers have so many time-outs and safety features, they need a large digital section to do all this, and the fact that there are so many different li-ion chemistries makes the digital nature of the chip great, since it is easy to tweak voltage and current levers over the charge cycle, as well as timeouts and temperature profiles. But it should be noted that the proponents of digital power are not simply talking about digital control and monitors, which for the most part is done around an analog PWM section. To most engineers, when you say digital power it means using either a DSP or a digital state machine to close the control loop and operate the PWM section.

It is reasonable to call this digital power since almost no other factor in the chips can be differentiated from an analog PWM chip. All the digital power vendors brag about phase shedding to conserve efficiency, but any analog power chip vendor could throw a couple of comparators into their chip and phase shed the analog control loops. So when it comes to predominate definition of digital power, a digital control loop, what should you be concerned about? Well, if you are a power supply user you should not care at all. To you it is totally irrelevant if the semiconductor manufacturer closes the loop digitally or with analog. All you care about is if the chip meets you specs and if it has the features you need. Now the semiconductor companies have a lot harder decision. A friend, Paul Greenland, formerly at National, gave me an insight into the digital power conundrum for a semiconductor company. He pointed out that he could architect a digital PWM section in a far smaller die area than an analog PWM section. Sounds great, until he pointed out that the mask cost for that digital PWM section was up to 5 times more expensive. When you say digital PWM you also imply some other problems, one being that this means you are using CMOS so you will not have the high-voltage transistors that many power systems need. This means the cost benefit of an integrated switcher will be lost since you have to have the controller be CMOS that feeds a driver that does the actual switching. Also, don’t expect the usual Moore’s law benefits. What good is 90 nm digital silicon if you only get 1-volt transistors? So then your digital power controller needs two rails of its own—one for the digital and a 5-volt rail for the output drivers. You should also note that the since you are stuck with large feature CMOS, (135 to 250 nm), that means that adding an A to D converter will take up far more space than you save from the PWM section. See, even digital chips have analog tradeoffs, in the sense that system-level design is always analog. In fact the smart people at Silicon Labs told me last year that they don’t necessarily use an A-to-D converter. Sometimes they use a DAC to make the set point voltage and then use a simple comparator to indicate when the supply is above or below the regulation point.

Does this mean digital PWM loop chips will never fly? Hardly, they are already in use. But do not look for them to replace every power chip the way the digital aficionados predicted a few years ago. Even using a DSP for digital power has advantages in some instances. As Dave Freeman from TI pointed out to me at last year’s conference, if you have a wind turbine that already has a DSP to do the three-phase power generation and the servo control on the pitch of the windmill blades, then adding a little code to make a power rail can be far cheaper than using a separate control chip. If you need many rails, like that ADI chip that has 7 PWM sections, well, that seems like a good candidate if the chip architect can give more sections without growing the die too far. But as I pointed out, these are all headaches for the semiconductor manufacturers, not us users of power supplies. Saying a part is digital power is as meaningless as Tide saying “New and Improved”. All that matters to the power supply engineer is what the chip can do at what cost. Whether loop is closed with 100 analog transistors or 10,000 state machine transistors or 60,000 DSP transistors, that is something for the semiconductor company to worry about, not us.

So my one recommendation is do not think that digital is better than analog power because CDs are more popular than vinyl records. Look at what the power chip can do and evaluate if that is what you need. One of the things the digital power people do not seem to realize is the resistance most of us have to putting any software development effort in the power path. The ease of use of the modern development systems allays much of those fears but you will still have to document and control the chip programming, rather than just have a BOM with resistor and capacitor values. Also, do not think that digital power is the only way to achieve your goals. As Fairchild implied, you may be able to hang a 2-dollar micro on your system and have all the features that digital power can give you. And be sure to differentiate what is really digital power versus digital monitoring and control, something analog power chips have done for a decade. Indeed, after seeing so many presentations about the efficiency improvements possible with digital power I leaned over and got a little tutorial from National’s Dave Anderson. He confirmed the four loss terms I had written down and added FET losses due to the gate capacitance shunting current to ground. The other four are copper loses, magnetic or core losses due to eddy currents, R-on loss in the FET and switching loss in the FET due to the finite slew time where the FET is in the linear range. In reality a digital control loop cannot do anything about these losses other than the gross disabling of phases or perhaps some frequency modulation. But Vicor has used series resonant converters for over a decade and those are variable frequency. Slobodan Ĉuk down at Telsaco has a multiple magnetic converter that switches at 20 khz to minimize those FET gate losses. Now there is some work by college professors trying to gain efficiency in the digital control loop, but if you think about it, all the first-order terms are determined by the copper, the iron, the FETs you use, and how fast you turn them on and off.

Digital power has suffered from being a “push” technology dreamed up by college professors and semiconductor companies as opposed to a pull technology asked for by customers. There are definite applications for digital power; indeed, I wonder why they don’t change the name of this conference to the data-center power conference. Digital power will be much slower in its adaptation than all the people that thought they would get rich in a startup company. When I asked an FAE buddy that works for a company that sells both analog an digital power, he shrugs and remarks, “no market”. In other words, there still is no mass market willing to pay a price premium for a digital control loop, when an analog loop surrounded by digital management can do the same thing. The way I see it all the starry eyed digital guys that thought the whole power supply world would go digital are now traveling though the five phases of grief. Two years ago it was denial. They were sure their chips were better and could not understand why they were mot selling. Last year it was anger. The companies were mad at us analog dinosaurs that did not buy these cool digital power chips. This year we are in the bargaining phase. They see that digital power has limited applications and hope that technology will allow the costs to come down to compete with analog. I expect next year will be the depression phase when everybody realizes that digital power is a good thing but not the only way to design a power chip. Two years from now will come acceptance, when the semiconductor companies see that digital power is a good way to solve a few problems in the very fragmented power market, but they won’t be tossing out their analog chip designers anytime soon. Like the Gartner hype cycle, the promise of digital power was way oversold, but when you look at the Gartner chart, you see the new technology will also end up ahead of where it started, even if it had to fall a bit from the high expectations.

Accordingly you should be agonistic about digital power. Think about your system needs, realize that a digital power chip may need to boot up or have different behaviors in corner cases, but be sure to look at this new way to close a loop. As those college professor’s keep working on sophisticated algorithms there will be a constant improvement in what digital power can do for you.